ARM: at91: clock: add a new file to handle clock

To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Wenyou Yang 2016-02-03 10:16:48 +08:00 committed by Andreas Bießmann
parent e5322df4e7
commit 41bf25c2e1
5 changed files with 69 additions and 33 deletions

View File

@ -15,6 +15,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
endif
obj-y += clock.o
obj-$(CONFIG_CPU_ARM920T) += arm920t/
obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
obj-$(CONFIG_CPU_V7) += armv7/

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@ -242,10 +242,3 @@ void at91_mck_init(u32 mckr)
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
;
}
void at91_periph_clk_enable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << id, &pmc->pcer);
}

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@ -150,32 +150,6 @@ void at91_mck_init(u32 mckr)
;
}
void at91_periph_clk_enable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 regval;
if (id > AT91_PMC_PCR_PID_MASK)
return;
regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
writel(regval, &pmc->pcr);
}
void at91_periph_clk_disable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 regval;
if (id > AT91_PMC_PCR_PID_MASK)
return;
regval = AT91_PMC_PCR_CMD_WRITE | id;
writel(regval, &pmc->pcr);
}
int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

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@ -0,0 +1,66 @@
/*
* Copyright (C) 2015 Atmel Corporation
* Wenyou Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
void at91_periph_clk_enable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#ifdef CPU_HAS_PCR
u32 regval;
u32 div_value;
if (id > AT91_PMC_PCR_PID_MASK)
return;
writel(id, &pmc->pcr);
div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
writel(regval, &pmc->pcr);
#else
writel(0x01 << id, &pmc->pcer);
#endif
}
void at91_periph_clk_disable(int id)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#ifdef CPU_HAS_PCR
u32 regval;
if (id > AT91_PMC_PCR_PID_MASK)
return;
regval = AT91_PMC_PCR_CMD_WRITE | id;
writel(regval, &pmc->pcr);
#else
writel(0x01 << id, &pmc->pcdr);
#endif
}
void at91_system_clk_enable(int sys_clk)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(sys_clk, &pmc->scer);
}
void at91_system_clk_disable(int sys_clk)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(sys_clk, &pmc->scdr);
}

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@ -128,5 +128,7 @@ void at91_periph_clk_enable(int id);
void at91_periph_clk_disable(int id);
int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
u32 at91_get_periph_generated_clk(u32 id);
void at91_system_clk_enable(int sys_clk);
void at91_system_clk_disable(int sys_clk);
#endif /* __ASM_ARM_ARCH_CLK_H__ */