ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate the peripheral's and system's clock handle code, shared with the SoCs with different ARM core. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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@ -15,6 +15,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
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obj-y += spl.o
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endif
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obj-y += clock.o
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obj-$(CONFIG_CPU_ARM920T) += arm920t/
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obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
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obj-$(CONFIG_CPU_V7) += armv7/
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@ -242,10 +242,3 @@ void at91_mck_init(u32 mckr)
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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}
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void at91_periph_clk_enable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(1 << id, &pmc->pcer);
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}
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@ -150,32 +150,6 @@ void at91_mck_init(u32 mckr)
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;
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}
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void at91_periph_clk_enable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 regval;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
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writel(regval, &pmc->pcr);
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}
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void at91_periph_clk_disable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 regval;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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regval = AT91_PMC_PCR_CMD_WRITE | id;
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writel(regval, &pmc->pcr);
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}
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int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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66
arch/arm/mach-at91/clock.c
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66
arch/arm/mach-at91/clock.c
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@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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void at91_periph_clk_enable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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#ifdef CPU_HAS_PCR
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u32 regval;
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u32 div_value;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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writel(id, &pmc->pcr);
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div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
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regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
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writel(regval, &pmc->pcr);
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#else
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writel(0x01 << id, &pmc->pcer);
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#endif
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}
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void at91_periph_clk_disable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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#ifdef CPU_HAS_PCR
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u32 regval;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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regval = AT91_PMC_PCR_CMD_WRITE | id;
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writel(regval, &pmc->pcr);
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#else
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writel(0x01 << id, &pmc->pcdr);
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#endif
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}
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void at91_system_clk_enable(int sys_clk)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(sys_clk, &pmc->scer);
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}
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void at91_system_clk_disable(int sys_clk)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(sys_clk, &pmc->scdr);
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}
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@ -128,5 +128,7 @@ void at91_periph_clk_enable(int id);
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void at91_periph_clk_disable(int id);
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int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
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u32 at91_get_periph_generated_clk(u32 id);
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void at91_system_clk_enable(int sys_clk);
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void at91_system_clk_disable(int sys_clk);
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#endif /* __ASM_ARM_ARCH_CLK_H__ */
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