leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge tag 'u-boot-imx-20210125' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
Changes for 2020.04
-------------------

- new board:
	Phytec phyCORE-i.MX8MP
	i.MX8MN Beacon EmbeddedWorks devkit

- Fixes:
	several nanbcb fixes
	fix for imx8mm_beacon
- further switch to distro boot commands
- DM:
	DM Ether for MX6UL

CI:

https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
This commit is contained in:
Tom Rini
2021-01-25 09:02:35 -05:00
parent 7f10b8eed4 4f37aa9579
commit 4057b98ff2
90 changed files with 10022 additions and 2340 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
board/beacon/imx8mn/Kconfig Normal file
View File

@@ -0,0 +1,18 @@
if TARGET_IMX8MN_BEACON
config SYS_BOARD
default "imx8mn"
config SYS_VENDOR
default "beacon"
config SYS_CONFIG_NAME
default "imx8mn_beacon"
config IMX8MN_FORCE_NOM_SOC
bool "Force to use nominal mode for SOC and ARM"
default n
source "board/freescale/common/Kconfig"
endif

6
board/beacon/imx8mn/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
i.MX8MN BEACON BOARD
M: Adam Ford <aford173@gmail.com>
S: Maintained
F: board/beacon/imx8mn/
F: include/configs/imx8mn_beacon.h
F: configs/imx8mn_beacon_defconfig

13
board/beacon/imx8mn/Makefile Normal file
View File

@@ -0,0 +1,13 @@
#
# Copyright 2020 Compass Electronics Group, LLC
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mn_beacon.o
obj-y += ../../freescale/common/
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
endif

39
board/beacon/imx8mn/README Normal file
View File

@@ -0,0 +1,39 @@
U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr firmware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
======================================
Note: $(srctree) is U-Boot source directory
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git checkout imx_5.4.47_2.2.0
$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mm/release/bl31.bin $(srctree)
Get the DDR firmware
====================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Build U-Boot
============
$ make imx8mn_beacon_defconfig
$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x960000
Burn U-Boot to microSD Card
===========================
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
Boot
====
Set baseboard DIP switch:
S17: 1100XXXX

56
board/beacon/imx8mn/imx8mn_beacon.c Normal file
View File

@@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#if IS_ENABLED(CONFIG_FEC_MXC)
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return CONFIG_SYS_MMC_ENV_DEV;
}

1434
board/beacon/imx8mn/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

128
board/beacon/imx8mn/spl.c Normal file
View File

@@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <common.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mn_pins.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/bd71837.h>
#include <spl.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
struct udevice *dev;
int ret;
debug("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0)
puts("Failed to find clock node. Check device tree\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(1);
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

35
board/freescale/imx8mm_evk/boot.cmd Normal file
View File

@@ -0,0 +1,35 @@
setenv bootargs console=${console} root=${mmcroot};
for boot_target in ${boot_targets};
do
if test "${boot_target}" = "mmc1" ; then
if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from SD card(mmc1);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
if test "${boot_target}" = "mmc2" ; then
if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from eMMC(mmc2);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
if test "${boot_target}" = "dhcp" ; then
if dhcp ${kernel_addr_r} ${serverip}:${image}; then
if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
echo Load image and .dtb from net(dhcp);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
done

2
board/freescale/imx8mn_evk/Kconfig
View File

@@ -1,4 +1,4 @@
if TARGET_IMX8MN_EVK
if TARGET_IMX8MN_DDR4_EVK
config SYS_BOARD
default "imx8mn_evk"

25
board/freescale/imx8mp_evk/boot.cmd Normal file
View File

@@ -0,0 +1,25 @@
setenv bootargs console=${console} root=${mmcroot};
for boot_target in ${boot_targets};
do
if test "${boot_target}" = "mmc1" ; then
if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from SD card(mmc1);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
if test "${boot_target}" = "mmc2" ; then
if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then
echo Load image and .dtb from eMMC(mmc2);
booti ${kernel_addr_r} - ${fdt_addr};
exit;
fi
fi
fi
done

65
board/freescale/imx8mp_evk/imx8mp_evk.c
View File

@@ -7,9 +7,13 @@
#include <env.h>
#include <errno.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
@@ -40,9 +44,68 @@ int board_early_init_f(void)
return 0;
}
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
}
#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
static iomux_v3_cfg_t const eqos_rst_pads[] = {
MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_eqos(void)
{
imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
ARRAY_SIZE(eqos_rst_pads));
gpio_request(EQOS_RST_PAD, "eqos_rst");
gpio_direction_output(EQOS_RST_PAD, 0);
mdelay(15);
gpio_direction_output(EQOS_RST_PAD, 1);
mdelay(100);
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_eqos();
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if CONFIG_IS_ENABLED(NET)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
return 0;
int ret = 0;
if (CONFIG_IS_ENABLED(FEC_MXC)) {
setup_fec();
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
ret = setup_eqos();
}
return ret;
}
int board_late_init(void)

12
board/phytec/phycore_imx8mp/Kconfig Normal file
View File

@@ -0,0 +1,12 @@
if TARGET_PHYCORE_IMX8MP
config SYS_BOARD
default "phycore_imx8mp"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_imx8mp"
endif

9
board/phytec/phycore_imx8mp/MAINTAINERS Normal file
View File

@@ -0,0 +1,9 @@
phyCORE-i.MX8M Plus
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
S: Maintained
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig
F: include/configs/phycore_imx8mp.h

11
board/phytec/phycore_imx8mp/Makefile Normal file
View File

@@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2020 PHYTEC Messtechnik GmbH
# Author: Teresa Remmet <t.remmet@phytec.de>
obj-y += phycore-imx8mp.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

1849
board/phytec/phycore_imx8mp/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

39
board/phytec/phycore_imx8mp/phycore-imx8mp.c Normal file
View File

@@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
switch (get_boot_device()) {
case SD2_BOOT:
env_set_ulong("mmcdev", 1);
break;
case MMC3_BOOT:
env_set_ulong("mmcdev", 2);
break;
default:
break;
}
return 0;
}

129
board/phytec/phycore_imx8mp/spl.c Normal file
View File

@@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
int power_init_board(void)
{
struct pmic *p;
int ret;
ret = power_pca9450_init(0);
if (ret)
printf("power init failed");
p = pmic_get("PCA9450");
pmic_probe(p);
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
/* increase VDD_SOC to typical value 0.95V */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
int board_fit_config_name_match(const char *name)
{
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
init_uart_clk(1);
board_early_init_f();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
}

76
board/variscite/dart_6ul/dart_6ul.c
View File

@@ -2,6 +2,7 @@
/*
* Copyright (C) 2015-2019 Variscite Ltd.
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
*/
#include <init.h>
@@ -18,9 +19,6 @@
#include <linux/bitops.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -97,67 +95,6 @@ static void setup_gpmi_nand(void)
#endif
#ifdef CONFIG_FEC_MXC
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST)
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_ODE)
/*
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
* be used for ENET1 or ENET2, cannot be used for both.
*/
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
{
if (fec_id == 0)
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
}
int board_eth_init(struct bd_info *bis)
{
int ret = 0;
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
/* USB Ethernet Gadget */
usb_eth_initialize(bis);
#endif
return ret;
}
static int setup_fec(int fec_id)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -203,13 +140,6 @@ int board_phy_config(struct phy_device *phydev)
}
#endif /* CONFIG_FEC_MXC */
int board_early_init_f(void)
{
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
@@ -250,7 +180,7 @@ struct dart6ul_info {
#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1)
#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3)
#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8)
#define DART6UL_DDRSIZE(n) ((n) * SZ_128M)
#define DART6UL_INFO_MAGIC 0x32524156
static const char *som_info_storage_to_str(u8 som_info)
@@ -323,7 +253,7 @@ int checkboard(void)
info->date,
som_info_storage_to_str(info->som_info),
DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
DART6UL_DDRSIZE_IN_MIB(info->ddr_size),
DART6UL_DDRSIZE(info->ddr_size) / SZ_1M,
som_info_rev_to_str(info->som_info));
free(info);

3
board/variscite/dart_6ul/spl.c
View File

@@ -199,9 +199,6 @@ void board_init_f(ulong dummy)
setup_iomux_uart();
/* iomux and setup of i2c */
board_early_init_f();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();