mx7d: Add Storopack's SMEGW01 board
Add support for Storopack's SMEGW01 board, which is an IoT gateway based on the i.MX7D SoC. Based on the original U-Boot work done by Phytec. Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
d4f15ecd47
commit
40496ac3b7
@ -834,8 +834,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
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imx7s-warp.dtb \
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imx7s-warp.dtb \
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imx7d-meerkat96.dtb \
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imx7d-meerkat96.dtb \
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imx7d-pico-pi.dtb \
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imx7d-pico-pi.dtb \
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imx7d-pico-hobbit.dtb
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imx7d-pico-hobbit.dtb \
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imx7d-smegw01.dtb
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
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imx7ulp-evk.dtb
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imx7ulp-evk.dtb
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190
arch/arm/dts/imx7d-smegw01.dts
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190
arch/arm/dts/imx7d-smegw01.dts
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@ -0,0 +1,190 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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//
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// Copyright (C) 2020 PHYTEC Messtechnik GmbH
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// Author: Jens Lang <J.Lang@phytec.de>
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// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "Storopack SMEGW01 board";
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compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
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aliases {
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mmc0 = &usdhc1;
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mmc1 = &usdhc3;
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};
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chosen {
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stdout-path = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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enable-sdio-wakeup;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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max-frequency = <200000000>;
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bus-width = <8>;
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fsl,tuning-step = <1>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-hs200-1_8v;
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mmc-ddr-1_8v;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
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MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
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>;
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};
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pinctrl_usdhc1: usdhc1 {
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fsl,pins = <
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
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MX7D_PAD_SD1_CMD__SD1_CMD 0x59
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MX7D_PAD_SD1_CLK__SD1_CLK 0x19
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MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
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MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
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MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
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MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
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>;
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};
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pinctrl_usdhc3: usdhc3 {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3_100mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
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MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3_200mhz {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
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MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
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>;
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};
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};
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@ -70,6 +70,14 @@ config TARGET_PICO_IMX7D
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select SUPPORT_SPL
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select SUPPORT_SPL
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imply CMD_DM
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imply CMD_DM
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config TARGET_SMEGW01
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bool "smegw01"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX7D
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imply CMD_DM
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config TARGET_WARP7
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config TARGET_WARP7
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bool "warp7"
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bool "warp7"
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select BOARD_LATE_INIT
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select BOARD_LATE_INIT
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@ -94,6 +102,7 @@ source "board/compulab/cl-som-imx7/Kconfig"
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source "board/ronetix/imx7-cm/Kconfig"
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source "board/ronetix/imx7-cm/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/novtech/meerkat96/Kconfig"
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source "board/novtech/meerkat96/Kconfig"
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source "board/storopack/smegw01/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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source "board/warp7/Kconfig"
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12
board/storopack/smegw01/Kconfig
Normal file
12
board/storopack/smegw01/Kconfig
Normal file
@ -0,0 +1,12 @@
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if TARGET_SMEGW01
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config SYS_BOARD
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default "smegw01"
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config SYS_VENDOR
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default "storopack"
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config SYS_CONFIG_NAME
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default "smegw01"
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endif
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7
board/storopack/smegw01/MAINTAINERS
Normal file
7
board/storopack/smegw01/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
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SMEGW01 BOARD
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M: Fabio Estevam <festevam@denx.de>
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S: Maintained
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F: board/storopack/
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F: arch/arm/dts/imx7d-smegw01.dts
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F: configs/smegw01_defconfig
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F: include/configs/smegw01.h
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4
board/storopack/smegw01/Makefile
Normal file
4
board/storopack/smegw01/Makefile
Normal file
@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2016 NXP Semiconductors
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obj-y := smegw01.o
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100
board/storopack/smegw01/imximage.cfg
Normal file
100
board/storopack/smegw01/imximage.cfg
Normal file
@ -0,0 +1,100 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 PHYTEC America, LLC
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*
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* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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IMAGE_VERSION 2
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* DDR initialization came from Phytec */
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DATA 4 0x30340004 0x4F400005
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x0040002b
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x090b1109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000802
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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||||||
|
DATA 4 0x307a0194 0x00030303
|
||||||
|
DATA 4 0x307a0200 0x00001f15
|
||||||
|
DATA 4 0x307a0204 0x00080808
|
||||||
|
DATA 4 0x307a0210 0x00000f0f
|
||||||
|
DATA 4 0x307a0214 0x07070707
|
||||||
|
DATA 4 0x307a0218 0x0f0f0707
|
||||||
|
DATA 4 0x307a0240 0x06000604
|
||||||
|
DATA 4 0x307a0244 0x00000001
|
||||||
|
DATA 4 0x30391000 0x00000000
|
||||||
|
DATA 4 0x30790000 0x17420f40
|
||||||
|
DATA 4 0x30790004 0x10210100
|
||||||
|
DATA 4 0x30790010 0x00060807
|
||||||
|
DATA 4 0x307900b0 0x1010007e
|
||||||
|
DATA 4 0x3079009c 0x00000d6e
|
||||||
|
DATA 4 0x30790020 0x0a0a0a0a
|
||||||
|
DATA 4 0x30790030 0x06060606
|
||||||
|
DATA 4 0x30790050 0x01000010
|
||||||
|
DATA 4 0x30790050 0x00000010
|
||||||
|
DATA 4 0x307900c0 0x0e407304
|
||||||
|
DATA 4 0x307900c0 0x0e447304
|
||||||
|
DATA 4 0x307900c0 0x0e447306
|
||||||
|
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||||
|
DATA 4 0x307900c0 0x0e447304
|
||||||
|
DATA 4 0x307900c0 0x0e407304
|
||||||
|
DATA 4 0x30384130 0x00000000
|
||||||
|
DATA 4 0x30340020 0x00000178
|
||||||
|
DATA 4 0x30384130 0x00000002
|
||||||
|
DATA 4 0x30790018 0x0000000f
|
||||||
|
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||||
95
board/storopack/smegw01/smegw01.c
Normal file
95
board/storopack/smegw01/smegw01.c
Normal file
@ -0,0 +1,95 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
|
||||||
|
|
||||||
|
#include <init.h>
|
||||||
|
#include <net.h>
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
#include <asm/arch/mx7-pins.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/global_data.h>
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/mach-imx/hab.h>
|
||||||
|
#include <asm/mach-imx/iomux-v3.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <env.h>
|
||||||
|
#include <asm/arch/crm_regs.h>
|
||||||
|
#include <asm/setup.h>
|
||||||
|
#include <asm/bootm.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
|
||||||
|
PAD_CTL_HYS)
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||||
|
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||||
|
};
|
||||||
|
|
||||||
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||||
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void setup_iomux_uart(void)
|
||||||
|
{
|
||||||
|
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||||
|
};
|
||||||
|
|
||||||
|
static int setup_fec(void)
|
||||||
|
{
|
||||||
|
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
|
||||||
|
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
|
||||||
|
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||||
|
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
|
||||||
|
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
|
||||||
|
|
||||||
|
ret = set_clk_enet(ENET_125MHZ);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
setup_iomux_uart();
|
||||||
|
setup_fec();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
/* address of boot parameters */
|
||||||
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_late_init(void)
|
||||||
|
{
|
||||||
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||||
|
|
||||||
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||||
|
|
||||||
|
set_wdog_reset(wdog);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
||||||
|
* since we use PMIC_PWRON to reset the board.
|
||||||
|
*/
|
||||||
|
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
63
configs/smegw01_defconfig
Normal file
63
configs/smegw01_defconfig
Normal file
@ -0,0 +1,63 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_MX7=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||||
|
CONFIG_SYS_MEMTEST_END=0xa0000000
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_OFFSET=0xC0000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_TARGET_SMEGW01=y
|
||||||
|
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||||
|
# CONFIG_ARMV7_VIRT is not set
|
||||||
|
CONFIG_IMX_RDC=y
|
||||||
|
CONFIG_IMX_BOOTAUX=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
|
||||||
|
CONFIG_FIT=y
|
||||||
|
CONFIG_FIT_VERBOSE=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/storopack/smegw01/imximage.cfg"
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
# CONFIG_CMD_BOOTD is not set
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
# CONFIG_CMD_IMI is not set
|
||||||
|
# CONFIG_CMD_XIMG is not set
|
||||||
|
CONFIG_CMD_MEMTEST=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_PART=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_BOUNCE_BUFFER=y
|
||||||
|
CONFIG_DFU_MMC=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_FSL_USDHC=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_MICREL=y
|
||||||
|
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
|
CONFIG_MII=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
CONFIG_DM_PMIC=y
|
||||||
|
CONFIG_DM_PMIC_PFUZE100=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_MXC_UART=y
|
||||||
|
CONFIG_IMX_THERMAL=y
|
||||||
63
include/configs/smegw01.h
Normal file
63
include/configs/smegw01.h
Normal file
@ -0,0 +1,63 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2016 NXP Semiconductors
|
||||||
|
* Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
|
||||||
|
*
|
||||||
|
* Configuration settings for the smegw01 board.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SMEGW01_CONFIG_H
|
||||||
|
#define __SMEGW01_CONFIG_H
|
||||||
|
|
||||||
|
#include "mx7_common.h"
|
||||||
|
#include <imximage.h>
|
||||||
|
|
||||||
|
#define PHYS_SDRAM_SIZE SZ_512M
|
||||||
|
|
||||||
|
/* Size of malloc() pool */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
|
||||||
|
|
||||||
|
/* MMC Config*/
|
||||||
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
|
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"image=zImage\0" \
|
||||||
|
"console=ttymxc0\0" \
|
||||||
|
"fdtfile=imx7d-smegw01.dtb\0" \
|
||||||
|
"fdt_addr=0x83000000\0" \
|
||||||
|
"bootm_size=0x10000000\0" \
|
||||||
|
"mmcdev=0\0" \
|
||||||
|
"mmcpart=1\0" \
|
||||||
|
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||||
|
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||||
|
"root=${mmcroot}\0" \
|
||||||
|
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||||
|
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
|
||||||
|
"mmcboot=echo Booting from mmc ...; " \
|
||||||
|
"run mmcargs; " \
|
||||||
|
"if run loadfdt; then " \
|
||||||
|
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||||
|
"fi;\0" \
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"if run loadimage; then " \
|
||||||
|
"run mmcboot; " \
|
||||||
|
"fi; " \
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
#define CONFIG_SYS_HZ 1000
|
||||||
|
|
||||||
|
/* Physical Memory Map */
|
||||||
|
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||||
|
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||||
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||||
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user