leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: Remove unnecessary instruction

Browse Source 
The add instruction on risc-v can have any three sources and targets, so there
is no need for an intermediate mov.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Sean Anderson
2020-01-27 16:39:44 -05:00
committed by Andes
parent 33a6259d72
commit 404339759e
1 changed files with 2 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/riscv/cpu/start.S
View File

@@ -359,9 +359,8 @@ relocate_secondary_harts:
call_board_init_r: call_board_init_r:
jal invalidate_icache_all jal invalidate_icache_all
jal flush_dcache_all jal flush_dcache_all
la t0, board_init_r la t0, board_init_r /* offset of board_init_r() */
mv t4, t0 /* offset of board_init_r() */ add t4, t0, t6 /* real address of board_init_r() */
add t4, t4, t6 /* real address of board_init_r() */
/* /*
* setup parameters for board_init_r * setup parameters for board_init_r
*/ */