leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Browse Source
This commit is contained in:
Tom Rini 2013-05-02 19:54:32 -04:00
commit 3fe0128540
28 changed files with 833 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -254,6 +254,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
puts("Work-around for Erratum PCIe-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
return 0;
}

18
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -281,14 +281,6 @@ unsigned long get_tbclk (void)
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable) enable_interrupts();
}
void
reset_85xx_watchdog(void)
{
@ -297,6 +289,16 @@ reset_85xx_watchdog(void)
*/
mtspr(SPRN_TSR, TSR_WIS);
}
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable)
enable_interrupts();
}
#endif /* CONFIG_WATCHDOG */
/*

14
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -623,6 +623,20 @@ skip_l2:
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
/* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
* multi-bit ECC errors which has impact on performance, so software
* should disable all ECC reporting from USB1 and USB2.
*/
if (IS_SVR_REV(get_svr(), 1, 0)) {
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
setbits_be32(&dcfg->ecccr1,
(DCSR_DCFG_ECC_DISABLE_USB1 |
DCSR_DCFG_ECC_DISABLE_USB2));
}
#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif

7
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -663,6 +663,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);

4
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -103,6 +103,10 @@ static const struct {
{ 22, 168, FSL_SRDS_BANK_3 },
{ 23, 169, FSL_SRDS_BANK_3 },
#endif
#if SRDS_MAX_BANK > 3
{ 24, 175, FSL_SRDS_BANK_4 },
{ 25, 176, FSL_SRDS_BANK_4 },
#endif
};
int serdes_get_lane_idx(int lane)

20
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View File

@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 2),
SET_QP_INFO(15, 16, 3, 3),
SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 2),
SET_QP_INFO(15, 16, 8, 3),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif

20
arch/powerpc/cpu/mpc85xx/p3041_ids.c
View File

@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 2),
SET_QP_INFO(15, 16, 3, 3),
SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(1, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 2),
SET_QP_INFO(15, 16, 8, 3),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif

20
arch/powerpc/cpu/mpc85xx/p5020_ids.c
View File

@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 0),
SET_QP_INFO(7, 8, 4, 1),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 0),
SET_QP_INFO(15, 16, 3, 1),
SET_QP_INFO(17, 18, 4, 0),
SET_QP_INFO(19, 20, 5, 1),
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 0),
SET_QP_INFO(7, 8, 4, 1),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 0),
SET_QP_INFO(15, 16, 8, 1),
SET_QP_INFO(17, 18, 9, 0),
SET_QP_INFO(19, 20, 10, 1),
};
#endif

20
arch/powerpc/cpu/mpc85xx/portals.c
View File

@ -30,11 +30,9 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
void setup_portals(void)
{
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
#ifdef CONFIG_FSL_CORENET
int i;
@ -166,6 +164,20 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
num = get_dpaa_liodn(dev, &liodns[0], id);
ret = fdt_setprop(blob, childoff, "fsl,liodn",
&liodns[0], sizeof(u32) * num);
if (!strncmp(name, "pme", 3)) {
u32 pme_rev1, pme_rev2;
ccsr_pme_t *pme_regs =
(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
ret = fdt_setprop(blob, childoff,
"fsl,pme-rev1", &pme_rev1, sizeof(u32));
if (ret < 0)
return ret;
ret = fdt_setprop(blob, childoff,
"fsl,pme-rev2", &pme_rev2, sizeof(u32));
}
#endif
} else {
return childoff;
@ -183,6 +195,7 @@ void fdt_fixup_qportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
u32 rev_1 = in_be32(&qman->ip_rev_1);
u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
@ -272,6 +285,7 @@ void fdt_fixup_bportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
u32 rev_1 = in_be32(&bman->ip_rev_1);
u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];

12
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -333,7 +333,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -365,7 +367,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -442,6 +446,8 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -473,7 +479,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB138
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_ERRATUM_A004699
@ -490,7 +496,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_BSC9132)
@ -503,7 +508,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@ -560,6 +564,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)
@ -585,6 +590,7 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#else

4
arch/powerpc/include/asm/fsl_memac.h
View File

@ -222,6 +222,10 @@ struct memac {
/* IF_MODE - Interface Mode Register */
#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */

12
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2914,7 +2914,8 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
&& !defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
@ -3160,4 +3161,13 @@ struct ccsr_cluster_l2 {
#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
struct dcsr_dcfg_regs {
u8 res_0[0x520];
u32 ecccr1;
#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
#endif /*__IMMAP_85xx__*/

19
board/freescale/b4860qds/tlb.c
View File

@ -111,8 +111,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@ -122,6 +120,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_4K, 1),
/*
* *I*G - SRIO
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for SRIO2.
*/
#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
/* *I*G* - SRIO1 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
/* *I*G* - SRIO2 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_256M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

6
board/freescale/common/Makefile
View File

@ -33,10 +33,14 @@ COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FMAN_ENET) += fman.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
endif
COBJS-$(CONFIG_FSL_QIXIS) += qixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
endif
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
ifndef CONFIG_RAMBOOT_PBL
COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
@ -48,7 +52,9 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
endif
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o

26
board/freescale/common/cds_pci_ft.c
View File

@ -31,7 +31,8 @@ static void cds_pci_fixup(void *blob)
int node;
const char *path;
int len, slot, i;
u32 *map = NULL;
u32 *map = NULL, *piccells = NULL;
int off, cells;
node = fdt_path_offset(blob, "/aliases");
if (node >= 0) {
@ -41,6 +42,25 @@ static void cds_pci_fixup(void *blob)
if (node >= 0) {
map = fdt_getprop_w(blob, node, "interrupt-map", &len);
}
/* Each item in "interrupt-map" property is translated with
* following cells:
* PCI #address-cells, PCI #interrupt-cells,
* PIC address, PIC #address-cells, PIC #interrupt-cells.
*/
cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
if (off <= 0)
return;
cells += 1;
piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
if (piccells == NULL)
return;
cells += *piccells;
piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
if (piccells == NULL)
return;
cells += *piccells;
}
}
@ -49,12 +69,12 @@ static void cds_pci_fixup(void *blob)
slot = get_pci_slot();
for (i=0;i<len;i+=7) {
for (i=0;i<len;i+=cells) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
map+=7;
map+=cells;
}
}
}

2
board/freescale/p1010rdb/p1010rdb.c
View File

@ -217,7 +217,7 @@ void fdt_del_flexcan(void *blob)
int nodeoff = 0;
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"fsl,flexcan-v1.0")) >= 0) {
"fsl,p1010-flexcan")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}

14
board/freescale/p1022ds/Makefile
View File

@ -11,12 +11,26 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
COBJS-y += spl_minimal.o tlb.o law.o
else
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))

1
board/freescale/p1022ds/law.c
View File

@ -16,6 +16,7 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

129
board/freescale/p1022ds/spl_minimal.c Normal file
View File

@ -0,0 +1,129 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
void sdram_init(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
#endif
__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
/* Set, but do not enable the memory */
__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
&ddr->sdram_cfg);
in_be32(&ddr->sdram_cfg);
udelay(500);
/* Let the controller go */
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
in_be32(&ddr->sdram_cfg);
set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
}
const static u32 sysclk_tbl[] = {
66666000, 7499900, 83332500, 8999900,
99999000, 11111000, 12499800, 13333200
};
void board_init_f(ulong bootflag)
{
int px_spd;
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* for FPGA */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
/* initialize selected port with appropriate baud rate */
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
bus_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* Initialize the DDR3 */
sdram_init();
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0,
CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

20
board/freescale/p1022ds/tlb.c
View File

@ -41,6 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@ -67,24 +68,31 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC/eSPI/NAND boot */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
/* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
/* map the second 1G */
/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

66
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -55,6 +55,13 @@
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#define GPIO_DDR_RST_PORT 1
#define GPIO_DDR_RST_PIN 8
#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
#endif
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
#define PCA_IOPORT_I2C_ADDR 0x23
@ -67,7 +74,7 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
#if 0
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
@ -159,6 +166,16 @@ void board_gpio_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
/* reset DDR3 */
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
/* disable CE_PB8 */
clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
#endif
/* Enable VSC7385 switch */
setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
@ -421,6 +438,8 @@ void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
const char *soc_usb_compat = "fsl-usb2-dr";
int err, usb1_off, usb2_off;
ft_cpu_setup(blob, bd);
@ -442,5 +461,50 @@ void ft_board_setup(void *blob, bd_t *bd)
#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
const char *soc_elbc_compat = "fsl,p1020-elbc";
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
soc_elbc_compat,
fdt_strerror(off));
return;
}
err = fdt_del_node(blob, off);
if (err < 0) {
printf("WARNING: could not remove %s: %s.\n",
soc_elbc_compat, fdt_strerror(err));
}
return;
}
#endif
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
if (usb1_off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
soc_usb_compat,
fdt_strerror(usb1_off));
return;
}
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
soc_usb_compat);
if (usb2_off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
soc_usb_compat,
fdt_strerror(usb2_off));
return;
}
err = fdt_del_node(blob, usb2_off);
if (err < 0) {
printf("WARNING: could not remove %s: %s.\n",
soc_usb_compat, fdt_strerror(err));
}
}
#endif

15
board/freescale/p1_p2_rdb_pc/spl_minimal.c
View File

@ -81,6 +81,8 @@ void board_init_f(ulong bootflag)
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifndef CONFIG_QE
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
#elif defined(CONFIG_P1021RDB)
par_io_t *par_io = (par_io_t *)&(gur->qe_par_io);
#endif
/* initialize selected port with appropriate baud rate */
@ -102,6 +104,19 @@ void board_init_f(ulong bootflag)
__raw_writel(0x00200000, &pgpio->gpdat);
udelay(1000);
__raw_writel(0x00000000, &pgpio->gpdir);
#elif defined(CONFIG_P1021RDB)
/* init DDR3 reset signal CE_PB8 */
out_be32(&par_io[1].cpdir1, 0x00004000);
out_be32(&par_io[1].cpodr, 0x00800000);
out_be32(&par_io[1].cppar1, 0x00000000);
/* reset DDR3 */
out_be32(&par_io[1].cpdat, 0x00800000);
udelay(1000);
out_be32(&par_io[1].cpdat, 0x00000000);
udelay(1000);
out_be32(&par_io[1].cpdat, 0x00800000);
/* disable the CE_PB8 */
out_be32(&par_io[1].cpdir1, 0x00000000);
#endif
#ifndef CONFIG_SYS_INIT_L2_ADDR

2
boards.cfg
View File

@ -811,6 +811,8 @@ P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freesca
P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds freescale
P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND
P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND
P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH
P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH
P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD

199
doc/README.p1010rdb Normal file
View File

@ -0,0 +1,199 @@
Overview
=========
The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
The P1010 is a cost-effective, low-power, highly integrated host processor
based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
that addresses the requirements of several routing, gateways, storage, consumer,
and industrial applications. Applications of interest include the main CPUs and
I/O processors in network attached storage (NAS), the voice over IP (VoIP)
router/gateway, and wireless LAN (WLAN) and industrial controllers.
The P1010RDB board features are as follows:
Memory subsystem:
- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- 32 Mbyte NOR flash single-chip memory
- 32 Mbyte NAND flash memory
- 256 Kbit M24256 I2C EEPROM
- 16 Mbyte SPI memory
- I2C Board EEPROM 128x8 bit memory
- SD/MMC connector to interface with the SD memory card
Interfaces:
- PCIe:
- Lane0: x1 mini-PCIe slot
- Lane1: x1 PCIe standard slot
- SATA:
- 1 internal SATA connector to 2.5" 160G SATA2 HDD
- 1 eSATA connector to rear panel
- 10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
- USB 2.0 port:
- x1 USB2.0 port: via an ULPI PHY to micro-AB connector
- x1 USB2.0 poort via an internal PHY to micro-AB connector
- FlexCAN ports:
- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
interface;
- DUART interface:
- DUART interface: supports two UARTs up to 115200 bps for
console display
- J45 connectors are used for these 2 UART ports.
- TDM
- 2 FXS ports connected via an external SLIC to the TDM
interface. SLIC is controllled via SPI.
- 1 FXO port connected via a relay to FXS for switchover to
POTS
Board connectors:
- Mini-ITX power supply connector
- JTAG/COP for debugging
IEEE Std. 1588 signals for test and measurement
Real-time clock on I2C bus
POR
- support critical POR setting changed via switch on board
PCB
- 6-layer routing (4-layer signals, 2-layer power and ground)
Serial Port Configuration on P1010RDB
=====================================
Configure the serial port of the attached computer with the following values:
-Data rate: 115200 bps
-Number of data bits: 8
-Parity: None
-Number of Stop bits: 1
-Flow Control: Hardware/None
Settings of DIP-switch
======================
SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
Note: 1 stands for 'on', 0 stands for 'off'
Setting of hwconfig
===================
If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
instead of to CAN/UART1.
Build and burn u-boot to NOR flash
==================================
1. Build u-boot.bin image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make P1010RDB_NOR
2. Burn u-boot.bin into NOR flash
=> tftp $loadaddr $uboot
=> protect off eff80000 +$filesize
=> erase eff80000 +$filesize
=> cp.b $loadaddr eff80000 $filesize
3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
Alternate NOR bank
============================
1. Burn u-boot.bin into alternate NOR bank
=> tftp $loadaddr $uboot
=> protect off eef80000 +$filesize
=> erase eef80000 +$filesize
=> cp.b $loadaddr eef80000 $filesize
2. Switch to alternate NOR bank
=> mw.b ffb00009 1
=> reset
or set SW1[8]= ON
SW1[8]= OFF: Upper bank used for booting start
SW1[8]= ON: Lower bank used for booting start
CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
0 - boot from upper 4 sectors
1 - boot from lower 4 sectors
Build and burn u-boot to NAND flash
===================================
1. Build u-boot.bin image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make P1010RDB_NAND
2. Burn u-boot-nand.bin into NAND flash
=> tftp $loadaddr $uboot-nand
=> nand erase 0 $filesize
=> nand write $loadaddr 0 $filesize
3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
Build and burn u-boot to SPI flash
==================================
1. Build u-boot-spi.bin image
make P1010RDB_SPIFLASH_config; make
Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
Download u-boot.bin to linux and you can find some config files
under /usr/share such as config_xx.dat. Do below command:
boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
u-boot-spi.bin
to generate u-boot-spi.bin.
2. Burn u-boot-spi.bin into SPI flash
=> tftp $loadaddr $uboot-spi
=> sf erase 0 100000
=> sf write $loadaddr 0 $filesize
3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
CPLD POR setting registers
==========================
1. Set POR switch selection register (addr 0xFFB00011) to 0.
2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
proper values.
If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
switch command by I2C.
3. Send reset command.
After reset, the new POR setting will be implemented.
Two examples are given in below:
Switch from NOR to NAND boot with default frequency:
=> i2c dev 0
=> i2c mw 18 1 f9
=> i2c mw 18 3 f0
=> mw.b ffb00011 0
=> mw.b ffb00017 1
=> reset
Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
=> i2c dev 0
=> i2c mw 18 1 f1
=> i2c mw 18 3 f0
=> mw.b ffb00011 0
=> mw.b ffb00014 2
=> mw.b ffb00015 5
=> mw.b ffb00016 3
=> mw.b ffb00017 f
=> reset
Boot Linux from network using TFTP on P1010RDB
==============================================
Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
=> tftp 1000000 uImage
=> tftp 2000000 p1010rdb.dtb
=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
=> bootm 1000000 3000000 2000000
Please contact your local field applications engineer or sales representative
to obtain related documents, such as P1010-RDB User Guide for details.

102
doc/README.ramboot-ppc85xx Normal file
View File

@ -0,0 +1,102 @@
RAMBOOT for MPC85xx Platforms
==============================
RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
pre-mechanism is required to load the DDR with the bootloader binary.
- In case of SD and SPI boot this is done by BootROM code inside the chip
itself.
- In case of NAND boot FCM supports loading initial 4K code from NAND flash
which can initialize the DDR and get the complete bootloader copied to DDR.
In addition to the above there could be some more methods to initialize the DDR
and load it manually.
Two of them are described below.There is also an explanation as to where these
methods could be handy.
1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
execute the bootloader from DDR.
This may be handy in the following cases:
- In very early stage of platform bringup where other boot options are not
functional because of various reasons.
- In case the support to program the flashes on the board is not available.
2. Load the RAM based bootloader onto DDR using already existing bootloader on
the board.And then execute the bootloader from DDR.
Some usecases where this may be used:
- While developing some new feature of u-boot, for example USB driver or
SPI driver.
Suppose the board already has a working bootloader on it. And you would
prefer to keep it intact, at the same time want to test your bootloader.
In this case you can get your test bootloader binary into DDR via tftp
for example. Then execute the test bootloader.
- Suppose a platform already has a propreitery bootloader which does not
support for example AMP boot. In this case also RAM boot loader can be
utilized.
So basically when the original bootloader is required to be kept intact
RAM based bootloader can offer an updated bootloader on the system.
Both the above Bootloaders are slight variants of SDcard or SPI Flash
bootloader or for that matter even NAND bootloader.
All of them define CONFIG_SYS_RAMBOOT.
The main difference among all of them is the way the pre-environment is getting
configured and who is doing that.
- In case of SD card and SPI flash bootloader this is done by On Chip BootROM inside the Si itself.
- In case of NAND boot SPL/TPL code does it with some support from Si itself.
- In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing bootloader.
How to use them:
1. Using JTAG
Boot up in core hold off mode or stop the core after reset using JTAG
interface.
Preconfigure DDR/L2SRAM through JTAG interface.
- setup DDR controller registers.
- setup DDR LAWs
- setup DDR TLB
Load the RAM based boot loader to the proper location in DDR/L2SRAM.
set up IAR (Instruction counter properly)
Enable the core to execute.
2. Using already existing bootloader.
get the rambased boot loader binary into DDR/L2SRAM via tftp.
execute the RAM based bootloader.
=> tftp 11000000 u-boot-ram.bin
=> go 1107f000
Please note that L2SRAM can also be used instead of DDR if the SOC has
sufficient size of L2SRAM.
Necessary Code changes Required:
=====================================
Please note that below mentioned changes are for 85xx platforms.
They have been tested on P1020/P2020/P1010 RDB.
The main difference between the above two methods from technical perspective is
that in 1st case SOC is just out of reset so it is in default configuration.
(CCSRBAR is at 0xff700000).
In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
1. File name-> boards.cfg
There can be added specific Make options for RAMBoot. We can keep different
options for the two cases mentioned above.
for example
P1020RDB_JTAG_RAMBOOT and P1020RDB_GO_RAMBOOT.
2. platform config file
for example include/configs/P1_P2_RDB.h
#ifdef CONFIG_RAMBOOT
#define CONFIG_SDCARD
#endif
This will finally use the CONFIG_SYS_RAMBOOT.
3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
In the section of the particular SOC, for example P1020,
#if defined(CONFIG_GO)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
#else
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#endif
For JTAG RAMBOOT this is not required because CCSRBAR is at ff700000.

17
drivers/net/fm/memac.c
View File

@ -112,6 +112,23 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
/* Enable automatic speed selection */
if_mode |= IF_MODE_EN_AUTO;
if (type == PHY_INTERFACE_MODE_RGMII) {
if_mode &= ~IF_MODE_EN_AUTO;
if_mode &= ~IF_MODE_SETSP_MASK;
switch (speed) {
case SPEED_1000:
if_mode |= IF_MODE_SETSP_1000M;
break;
case SPEED_100:
if_mode |= IF_MODE_SETSP_100M;
break;
case SPEED_10:
if_mode |= IF_MODE_SETSP_10M;
default:
break;
}
}
debug(" %s, if_mode = %x\n", __func__, if_mode);
debug(" %s, if_status = %x\n", __func__, if_status);
out_be32(&regs->if_mode, if_mode);

132
include/configs/P1022DS.h
View File

@ -34,6 +34,29 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
#define CONFIG_NAND_FSL_ELBC
#ifdef CONFIG_NAND
#define CONFIG_SPL
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xfffff000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
@ -84,6 +107,13 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
SPL code*/
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
@ -105,6 +135,30 @@
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 2048
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
#define CONFIG_SYS_DDR_TIMING_3 0x00010000
#define CONFIG_SYS_DDR_TIMING_0 0x40110104
#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
#define CONFIG_SYS_DDR_MODE_1 0x00441221
#define CONFIG_SYS_DDR_MODE_2 0x00000000
#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
#define CONFIG_SYS_DDR_CONTROL 0xc7000008
#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
#define CONFIG_SYS_DDR_TIMING_4 0x00220001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
/*
* Memory map
*
@ -118,6 +172,7 @@
* Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
* 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
@ -126,38 +181,84 @@
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
#ifdef CONFIG_NAND
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#endif
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#ifndef CONFIG_SYS_MONITOR_BASE
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Nand Flash */
#if defined(CONFIG_NAND_FSL_ELBC)
#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#else
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
@ -177,6 +278,8 @@
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xF0
#define PIXIS_LBMAP_ALTBANK 0x20
#define PIXIS_SPD 0x07
#define PIXIS_SPD_SYSCLK_MASK 0x07
#define PIXIS_ELBC_SPI_MASK 0xc0
#define PIXIS_SPI 0x80
@ -199,6 +302,9 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@ -419,7 +525,6 @@
/*
* Environment
*/
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
@ -433,16 +538,15 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_NAND_U_BOOT)
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#else
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000

1
include/configs/corenet_ds.h
View File

@ -714,6 +714,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \