reset: zynqmp: Add reset controller for ZynqMP SoC
Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
parent
8396700c33
commit
3f123b7424
@ -600,6 +600,7 @@ F: drivers/mtd/nand/raw/zynq_nand.c
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F: drivers/net/phy/xilinx_phy.c
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F: drivers/net/zynq_gem.c
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F: drivers/serial/serial_zynq.c
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F: drivers/reset/reset-zynqmp.c
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F: drivers/rtc/zynqmp_rtc.c
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F: drivers/spi/zynq_qspi.c
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F: drivers/spi/zynq_spi.c
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@ -197,4 +197,13 @@ config RESET_SCMI
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Enable this option if you want to support reset controller
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devices exposed by a SCMI agent based on SCMI reset domain
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protocol communication with a SCMI server.
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config RESET_ZYNQMP
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bool "Reset Driver for Xilinx ZynqMP SoC's"
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depends on DM_RESET && ZYNQMP_FIRMWARE
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help
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Support for reset controller on Xilinx ZynqMP SoC. Driver is only
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passing request via Xilinx firmware interface to TF-A and PMU
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firmware.
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endmenu
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@ -29,3 +29,4 @@ obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
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obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
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100
drivers/reset/reset-zynqmp.c
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100
drivers/reset/reset-zynqmp.c
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Xilinx, Inc. - Michal Simek
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*/
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#define LOG_CATEGORY UCLASS_RESET
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <reset-uclass.h>
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#include <zynqmp_firmware.h>
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#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
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#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
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struct zynqmp_reset_priv {
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u32 reset_id;
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u32 nr_reset;
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};
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static int zynqmp_pm_reset_assert(const u32 reset,
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const enum zynqmp_pm_reset_action assert_flag)
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{
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return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0,
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NULL);
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}
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static int zynqmp_reset_assert(struct reset_ctl *rst)
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{
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struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
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dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
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return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
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PM_RESET_ACTION_ASSERT);
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}
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static int zynqmp_reset_deassert(struct reset_ctl *rst)
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{
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struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
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dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
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return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
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PM_RESET_ACTION_RELEASE);
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}
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static int zynqmp_reset_request(struct reset_ctl *rst)
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{
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struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
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dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
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rst, rst->id, priv->nr_reset);
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if (rst->id > priv->nr_reset)
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return -EINVAL;
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return 0;
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}
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static int zynqmp_reset_free(struct reset_ctl *rst)
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{
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struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
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dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
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rst, rst->id, priv->nr_reset);
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return 0;
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}
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static int zynqmp_reset_probe(struct udevice *dev)
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{
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struct zynqmp_reset_priv *priv = dev_get_priv(dev);
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priv->reset_id = ZYNQMP_RESET_ID;
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priv->nr_reset = ZYNQMP_NR_RESETS;
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return 0;
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}
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const struct reset_ops zynqmp_reset_ops = {
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.request = zynqmp_reset_request,
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.rfree = zynqmp_reset_free,
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.rst_assert = zynqmp_reset_assert,
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.rst_deassert = zynqmp_reset_deassert,
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};
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static const struct udevice_id zynqmp_reset_ids[] = {
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{ .compatible = "xlnx,zynqmp-reset" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_reset) = {
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.name = "zynqmp_reset",
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.id = UCLASS_RESET,
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.of_match = zynqmp_reset_ids,
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.ops = &zynqmp_reset_ops,
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.probe = zynqmp_reset_probe,
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.priv_auto = sizeof(struct zynqmp_reset_priv),
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};
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@ -84,6 +84,137 @@ enum pm_query_id {
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PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
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};
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enum zynqmp_pm_reset_action {
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PM_RESET_ACTION_RELEASE = 0,
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PM_RESET_ACTION_ASSERT = 1,
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PM_RESET_ACTION_PULSE = 2,
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};
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enum zynqmp_pm_reset {
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ZYNQMP_PM_RESET_START = 1000,
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ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
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ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
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ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
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ZYNQMP_PM_RESET_DP = 1003,
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ZYNQMP_PM_RESET_SWDT_CRF = 1004,
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ZYNQMP_PM_RESET_AFI_FM5 = 1005,
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ZYNQMP_PM_RESET_AFI_FM4 = 1006,
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ZYNQMP_PM_RESET_AFI_FM3 = 1007,
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ZYNQMP_PM_RESET_AFI_FM2 = 1008,
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ZYNQMP_PM_RESET_AFI_FM1 = 1009,
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ZYNQMP_PM_RESET_AFI_FM0 = 1010,
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ZYNQMP_PM_RESET_GDMA = 1011,
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ZYNQMP_PM_RESET_GPU_PP1 = 1012,
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ZYNQMP_PM_RESET_GPU_PP0 = 1013,
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ZYNQMP_PM_RESET_GPU = 1014,
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ZYNQMP_PM_RESET_GT = 1015,
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ZYNQMP_PM_RESET_SATA = 1016,
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ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
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ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
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ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
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ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
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ZYNQMP_PM_RESET_APU_L2 = 1021,
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ZYNQMP_PM_RESET_ACPU3 = 1022,
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ZYNQMP_PM_RESET_ACPU2 = 1023,
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ZYNQMP_PM_RESET_ACPU1 = 1024,
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ZYNQMP_PM_RESET_ACPU0 = 1025,
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ZYNQMP_PM_RESET_DDR = 1026,
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ZYNQMP_PM_RESET_APM_FPD = 1027,
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ZYNQMP_PM_RESET_SOFT = 1028,
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ZYNQMP_PM_RESET_GEM0 = 1029,
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ZYNQMP_PM_RESET_GEM1 = 1030,
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ZYNQMP_PM_RESET_GEM2 = 1031,
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ZYNQMP_PM_RESET_GEM3 = 1032,
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ZYNQMP_PM_RESET_QSPI = 1033,
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ZYNQMP_PM_RESET_UART0 = 1034,
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ZYNQMP_PM_RESET_UART1 = 1035,
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ZYNQMP_PM_RESET_SPI0 = 1036,
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ZYNQMP_PM_RESET_SPI1 = 1037,
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ZYNQMP_PM_RESET_SDIO0 = 1038,
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ZYNQMP_PM_RESET_SDIO1 = 1039,
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ZYNQMP_PM_RESET_CAN0 = 1040,
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ZYNQMP_PM_RESET_CAN1 = 1041,
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ZYNQMP_PM_RESET_I2C0 = 1042,
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ZYNQMP_PM_RESET_I2C1 = 1043,
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ZYNQMP_PM_RESET_TTC0 = 1044,
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ZYNQMP_PM_RESET_TTC1 = 1045,
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ZYNQMP_PM_RESET_TTC2 = 1046,
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ZYNQMP_PM_RESET_TTC3 = 1047,
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ZYNQMP_PM_RESET_SWDT_CRL = 1048,
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ZYNQMP_PM_RESET_NAND = 1049,
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ZYNQMP_PM_RESET_ADMA = 1050,
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ZYNQMP_PM_RESET_GPIO = 1051,
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ZYNQMP_PM_RESET_IOU_CC = 1052,
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ZYNQMP_PM_RESET_TIMESTAMP = 1053,
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ZYNQMP_PM_RESET_RPU_R50 = 1054,
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ZYNQMP_PM_RESET_RPU_R51 = 1055,
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ZYNQMP_PM_RESET_RPU_AMBA = 1056,
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ZYNQMP_PM_RESET_OCM = 1057,
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ZYNQMP_PM_RESET_RPU_PGE = 1058,
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ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
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ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
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ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
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ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
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ZYNQMP_PM_RESET_USB0_APB = 1063,
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ZYNQMP_PM_RESET_USB1_APB = 1064,
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ZYNQMP_PM_RESET_IPI = 1065,
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ZYNQMP_PM_RESET_APM_LPD = 1066,
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ZYNQMP_PM_RESET_RTC = 1067,
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ZYNQMP_PM_RESET_SYSMON = 1068,
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ZYNQMP_PM_RESET_AFI_FM6 = 1069,
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ZYNQMP_PM_RESET_LPD_SWDT = 1070,
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ZYNQMP_PM_RESET_FPD = 1071,
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ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
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ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
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ZYNQMP_PM_RESET_DBG_LPD = 1074,
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ZYNQMP_PM_RESET_DBG_FPD = 1075,
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ZYNQMP_PM_RESET_APLL = 1076,
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ZYNQMP_PM_RESET_DPLL = 1077,
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ZYNQMP_PM_RESET_VPLL = 1078,
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ZYNQMP_PM_RESET_IOPLL = 1079,
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ZYNQMP_PM_RESET_RPLL = 1080,
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ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
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ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
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ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
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ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
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ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
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ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
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ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
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ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
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ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
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ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
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ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
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ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
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ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
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ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
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ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
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ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
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ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
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ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
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ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
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ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
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ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
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ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
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ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
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ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
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ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
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ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
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ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
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ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
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ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
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ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
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ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
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ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
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ZYNQMP_PM_RESET_RPU_LS = 1113,
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ZYNQMP_PM_RESET_PS_ONLY = 1114,
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ZYNQMP_PM_RESET_PL = 1115,
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ZYNQMP_PM_RESET_PS_PL0 = 1116,
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ZYNQMP_PM_RESET_PS_PL1 = 1117,
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ZYNQMP_PM_RESET_PS_PL2 = 1118,
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ZYNQMP_PM_RESET_PS_PL3 = 1119,
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ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
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};
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#define PM_SIP_SVC 0xc2000000
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#define ZYNQMP_PM_VERSION_MAJOR 1
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