global: Migrate CONFIG_SMP_PEN_ADDR to CFG
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
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@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
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bx lr
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ENDPROC(_nonsec_init)
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#ifdef CONFIG_SMP_PEN_ADDR
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#ifdef CFG_SMP_PEN_ADDR
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/* void __weak smp_waitloop(unsigned previous_address); */
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WEAK(smp_waitloop)
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wfi
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ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
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ldr r1, =CFG_SMP_PEN_ADDR @ load start address
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ldr r1, [r1]
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#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
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rev r1, r1
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@ -112,10 +112,10 @@ int checkboard(void)
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}
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#endif
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#ifdef CONFIG_SMP_PEN_ADDR
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#ifdef CFG_SMP_PEN_ADDR
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void smp_set_core_boot_addr(unsigned long addr, int corenr)
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{
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writel(addr, CONFIG_SMP_PEN_ADDR);
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writel(addr, CFG_SMP_PEN_ADDR);
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/* make sure this write is really executed */
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__asm__ volatile ("dsb\n");
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@ -16,7 +16,7 @@
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/* Miscellaneous configurable options */
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#define CONFIG_SMP_PEN_ADDR 0x02020000
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#define CFG_SMP_PEN_ADDR 0x02020000
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/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
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#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000
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@ -158,7 +158,7 @@
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{1, {I2C_NULL_HOP} }, \
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}
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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@ -68,7 +68,7 @@
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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@ -242,7 +242,7 @@
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* MMC
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*/
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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@ -133,7 +133,7 @@
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/* GPIO */
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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