Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx
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commit
3dd42fd5e2
@ -542,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd)
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#endif
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#ifdef CONFIG_PCIE1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
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@ -237,6 +237,6 @@ law_entry:
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/* contains both PCIE3 MEM & IO space */
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.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
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.long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
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4:
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entry_end
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@ -26,6 +26,7 @@
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/io.h>
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#include <spd.h>
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#include <miiphy.h>
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@ -222,6 +223,11 @@ pci_init_board(void)
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printf (" PCIE3 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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*/
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in_be32(CFG_PCIE3_MEM_BASE);
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} else {
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printf (" PCIE3: disabled\n");
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}
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@ -516,8 +522,16 @@ ft_board_setup(void *blob, bd_t *bd)
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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#ifdef CONFIG_PCI1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
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debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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#ifdef CONFIG_PCIE1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
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@ -525,7 +539,7 @@ ft_board_setup(void *blob, bd_t *bd)
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}
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#endif
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#ifdef CONFIG_PCIE2
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
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@ -533,7 +547,7 @@ ft_board_setup(void *blob, bd_t *bd)
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}
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#endif
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#ifdef CONFIG_PCIE3
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
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@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd)
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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#ifdef CONFIG_PCI1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
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debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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#ifdef CONFIG_PCI2
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
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debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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}
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#endif
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@ -310,6 +310,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CFG_PCIE3_IO_BASE 0x00000000
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#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
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#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
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#define CFG_PCIE3_MEM_BASE2 0xb0200000
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#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
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#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
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#if defined(CONFIG_PCI)
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