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net: gem: Do not setup any clock for Xilinx SoC Versal

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Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2018-08-22 16:18:34 +02:00
parent ec48b6c991
commit 3dc80934f4
1 changed files with 4 additions and 0 deletions
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4
drivers/net/zynq_gem.c
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@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev)
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
#else
debug("requested clk_rate %ld\n", clk_rate);
#endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);