Convert CONFIG_PCIE1 et al to Kconfig
This converts the following to Kconfig: CONFIG_PCIE1 CONFIG_PCIE2 CONFIG_PCIE3 CONFIG_PCIE4 CONFIG_PCI1 Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
a552ffc9d2
commit
3dc2987f5c
@ -138,6 +138,22 @@ config LAYERSCAPE_NS_ACCESS
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bool "Layerscape non-secure access support"
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depends on ARCH_LS1021A || FSL_LSCH2
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config PCIE1
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bool "PCIe controller #1"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE2
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bool "PCIe controller #2"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE3
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bool "PCIe controller #3"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE4
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bool "PCIe controller #4"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config FSL_USE_PCA9547_MUX
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bool "Enable PCA9547 I2C Mux on Freescale boards"
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depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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@ -1,5 +1,8 @@
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if TARGET_MPC8548CDS
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config PCI1
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def_bool y
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config SYS_BOARD
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default "mpc8548cds"
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@ -11,6 +11,7 @@ CONFIG_MPC85xx=y
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CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_PCIE1=y
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CONFIG_PHYS_64BIT=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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@ -11,6 +11,7 @@ CONFIG_MPC85xx=y
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CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_PCIE1=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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@ -12,6 +12,7 @@ CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_TARGET_MPC8548CDS_LEGACY=y
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CONFIG_PCIE1=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -10,6 +10,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -10,6 +10,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -10,6 +10,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -10,6 +10,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -11,6 +11,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -11,6 +11,8 @@ CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -11,6 +11,8 @@ CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -11,6 +11,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -17,6 +17,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -16,6 +16,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -18,6 +18,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -11,6 +11,8 @@ CONFIG_TARGET_P2020RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -8,6 +8,9 @@ CONFIG_MPC85xx=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PCIE3=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -8,6 +8,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P2041RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P2041RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P2041RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -15,6 +15,9 @@ CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -15,6 +15,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -17,6 +17,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -9,6 +9,9 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -14,6 +14,10 @@ CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -14,6 +14,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -16,6 +16,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,10 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -21,6 +21,20 @@ CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -21,6 +21,20 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -8,6 +8,10 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
|
@ -23,6 +23,20 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -2,6 +2,19 @@ CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_ENV_ADDR=0xFFE20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
|
@ -3,6 +3,18 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
|
||||
|
@ -18,6 +18,17 @@ CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -18,6 +18,17 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -20,6 +20,17 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -12,6 +12,17 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -19,6 +19,17 @@ CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -19,6 +19,17 @@ CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -21,6 +21,17 @@ CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -13,6 +13,17 @@ CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
@ -18,6 +18,17 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T4240RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -12,6 +12,17 @@ CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T4240RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
<<<<<<< HEAD
|
||||
=======
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PCIE3=y
|
||||
CONFIG_PCIE4=y
|
||||
CONFIG_VID=y
|
||||
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
|
||||
CONFIG_VOL_MONITOR_IR36021_READ=y
|
||||
CONFIG_VOL_MONITOR_IR36021_SET=y
|
||||
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
@ -12,6 +12,7 @@ CONFIG_TARGET_KMCENT2=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
# CONFIG_DEEP_SLEEP is not set
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_KM_DEF_NETDEV="eth2"
|
||||
CONFIG_KM_IVM_BUS=2
|
||||
CONFIG_MP=y
|
||||
|
@ -11,6 +11,7 @@ CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -13,6 +13,7 @@ CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_ENV_ADDR=0x401D0000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -13,6 +13,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -14,6 +14,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -13,6 +13,7 @@ CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
@ -13,6 +13,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
|
@ -12,6 +12,7 @@ CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -14,6 +14,7 @@ CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_ENV_ADDR=0x40300000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -14,6 +14,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x9fffffff
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
|
@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_AHCI=y
|
||||
# CONFIG_DEEP_SLEEP is not set
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_QSPI_BOOT=y
|
||||
|
@ -21,6 +21,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_AHCI=y
|
||||
# CONFIG_DEEP_SLEEP is not set
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_RAMBOOT_PBL=y
|
||||
|
@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_ENV_ADDR=0x60300000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_ENV_ADDR=0x60300000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
@ -22,6 +22,8 @@ CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
@ -15,6 +15,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_ENV_ADDR=0x60300000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
@ -16,6 +16,8 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
|
||||
CONFIG_ENV_ADDR=0x60300000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_LAYERSCAPE_NS_ACCESS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FSL_USE_PCA9547_MUX=y
|
||||
CONFIG_FSL_QIXIS=y
|
||||
# CONFIG_QIXIS_I2C_ACCESS is not set
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user