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x86: Add I/O APIC register access routines

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I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-06-23 12:18:49 +08:00 committed by Simon Glass
parent ba9091f55d
commit 3d23287828
3 changed files with 46 additions and 1 deletions
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2
arch/x86/cpu/Makefile
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@ -19,7 +19,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += irq.o lapic.o
obj-y += irq.o lapic.o ioapic.o
obj-$(CONFIG_SMP) += mp_init.o
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o

21
arch/x86/cpu/ioapic.c Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/ioapic.h>
u32 io_apic_read(u32 reg)
{
writel(reg, IO_APIC_INDEX);
return readl(IO_APIC_DATA);
}
void io_apic_write(u32 reg, u32 val)
{
writel(reg, IO_APIC_INDEX);
writel(val, IO_APIC_DATA);
}

24
arch/x86/include/asm/ioapic.h
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@ -15,4 +15,28 @@
#define IO_APIC_INDEX (IO_APIC_ADDR + 0x00)
#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
/* Indirect addressed register offset */
#define IO_APIC_ID 0x00
#define IO_APIC_VER 0x01
/**
* io_apic_read() - Read I/O APIC register
*
* This routine reads I/O APIC indirect addressed register.
*
* @reg: address of indirect addressed register
* @return: register value to read
*/
u32 io_apic_read(u32 reg);
/**
* io_apic_write() - Write I/O APIC register
*
* This routine writes I/O APIC indirect addressed register.
*
* @reg: address of indirect addressed register
* @val: register value to write
*/
void io_apic_write(u32 reg, u32 val);
#endif