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i2c: add Faraday FTI2C010 I2C controller support

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Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Heiko Schocher <hs@denx.de>
This commit is contained in:
Kuo-Jung Su 2013-05-08 15:36:26 +08:00 committed by Heiko Schocher
parent 30ea41a489
commit 3cff842bca
3 changed files with 451 additions and 0 deletions
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1
drivers/i2c/Makefile
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@ -44,6 +44,7 @@ COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o

369
drivers/i2c/fti2c010.c Normal file
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@ -0,0 +1,369 @@
/*
* Faraday I2C Controller
*
* (C) Copyright 2010 Faraday Technology
* Dante Su <dantesu@faraday-tech.com>
*
* This file is released under the terms of GPL v2 and any later version.
* See the file COPYING in the root directory of the source tree for details.
*/
#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include "fti2c010.h"
#ifndef CONFIG_HARD_I2C
#error "fti2c010: CONFIG_HARD_I2C is not defined"
#endif
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 50000
#endif
#ifndef CONFIG_FTI2C010_FREQ
#define CONFIG_FTI2C010_FREQ clk_get_rate("I2C")
#endif
/* command timeout */
#define CFG_CMD_TIMEOUT 10 /* ms */
/* 7-bit chip address + 1-bit read/write */
#define I2C_RD(chip) ((((chip) << 1) & 0xff) | 1)
#define I2C_WR(chip) (((chip) << 1) & 0xff)
struct fti2c010_chip {
void __iomem *regs;
uint bus;
uint speed;
};
static struct fti2c010_chip chip_list[] = {
{
.bus = 0,
.regs = (void __iomem *)CONFIG_FTI2C010_BASE,
},
#ifdef CONFIG_I2C_MULTI_BUS
# ifdef CONFIG_FTI2C010_BASE1
{
.bus = 1,
.regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
},
# endif
# ifdef CONFIG_FTI2C010_BASE2
{
.bus = 2,
.regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
},
# endif
# ifdef CONFIG_FTI2C010_BASE3
{
.bus = 3,
.regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
},
# endif
#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
};
static struct fti2c010_chip *curr = chip_list;
static int fti2c010_wait(uint32_t mask)
{
int ret = -1;
uint32_t stat, ts;
struct fti2c010_regs *regs = curr->regs;
for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
stat = readl(&regs->sr);
if ((stat & mask) == mask) {
ret = 0;
break;
}
}
return ret;
}
/*
* u-boot I2C API
*/
/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
void i2c_init(int speed, int slaveaddr)
{
if (speed || !curr->speed)
i2c_set_bus_speed(speed);
/* if slave mode disabled */
if (!slaveaddr)
return;
/*
* TODO:
* Implement slave mode, but is it really necessary?
*/
}
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
int i2c_probe(uchar chip)
{
int ret;
struct fti2c010_regs *regs = curr->regs;
i2c_init(0, 0);
/* 1. Select slave device (7bits Address + 1bit R/W) */
writel(I2C_WR(chip), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
/* 2. Select device register */
writel(0, &regs->dr);
writel(CR_ENABLE | CR_TBEN, &regs->cr);
ret = fti2c010_wait(SR_DT);
return ret;
}
/*
* Read/Write interface:
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
int ret, pos;
uchar paddr[4];
struct fti2c010_regs *regs = curr->regs;
i2c_init(0, 0);
paddr[0] = (addr >> 0) & 0xFF;
paddr[1] = (addr >> 8) & 0xFF;
paddr[2] = (addr >> 16) & 0xFF;
paddr[3] = (addr >> 24) & 0xFF;
/*
* Phase A. Set register address
*/
/* A.1 Select slave device (7bits Address + 1bit R/W) */
writel(I2C_WR(chip), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
/* A.2 Select device register */
for (pos = 0; pos < alen; ++pos) {
uint32_t ctrl = CR_ENABLE | CR_TBEN;
writel(paddr[pos], &regs->dr);
writel(ctrl, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
}
/*
* Phase B. Get register data
*/
/* B.1 Select slave device (7bits Address + 1bit R/W) */
writel(I2C_RD(chip), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
/* B.2 Get register data */
for (pos = 0; pos < len; ++pos) {
uint32_t ctrl = CR_ENABLE | CR_TBEN;
uint32_t stat = SR_DR;
if (pos == len - 1) {
ctrl |= CR_NAK | CR_STOP;
stat |= SR_ACK;
}
writel(ctrl, &regs->cr);
ret = fti2c010_wait(stat);
if (ret)
break;
buf[pos] = (uchar)(readl(&regs->dr) & 0xFF);
}
return ret;
}
/*
* Read/Write interface:
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
int ret, pos;
uchar paddr[4];
struct fti2c010_regs *regs = curr->regs;
i2c_init(0, 0);
paddr[0] = (addr >> 0) & 0xFF;
paddr[1] = (addr >> 8) & 0xFF;
paddr[2] = (addr >> 16) & 0xFF;
paddr[3] = (addr >> 24) & 0xFF;
/*
* Phase A. Set register address
*
* A.1 Select slave device (7bits Address + 1bit R/W)
*/
writel(I2C_WR(chip), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
/* A.2 Select device register */
for (pos = 0; pos < alen; ++pos) {
uint32_t ctrl = CR_ENABLE | CR_TBEN;
writel(paddr[pos], &regs->dr);
writel(ctrl, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
return ret;
}
/*
* Phase B. Set register data
*/
for (pos = 0; pos < len; ++pos) {
uint32_t ctrl = CR_ENABLE | CR_TBEN;
if (pos == len - 1)
ctrl |= CR_STOP;
writel(buf[pos], &regs->dr);
writel(ctrl, &regs->cr);
ret = fti2c010_wait(SR_DT);
if (ret)
break;
}
return ret;
}
/*
* Functions for setting the current I2C bus and its speed
*/
#ifdef CONFIG_I2C_MULTI_BUS
/*
* i2c_set_bus_num:
*
* Change the active I2C bus. Subsequent read/write calls will
* go to this one.
*
* bus - bus index, zero based
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_set_bus_num(uint bus)
{
if (bus >= ARRAY_SIZE(chip_list))
return -1;
curr = chip_list + bus;
i2c_init(0, 0);
return 0;
}
/*
* i2c_get_bus_num:
*
* Returns index of currently active I2C bus. Zero-based.
*/
uint i2c_get_bus_num(void)
{
return curr->bus;
}
#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
/*
* i2c_set_bus_speed:
*
* Change the speed of the active I2C bus
*
* speed - bus speed in Hz
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_set_bus_speed(uint speed)
{
struct fti2c010_regs *regs = curr->regs;
uint clk = CONFIG_FTI2C010_FREQ;
uint gsr = 0, tsr = 32;
uint spd, div;
if (!speed)
speed = CONFIG_SYS_I2C_SPEED;
for (div = 0; div < 0x3ffff; ++div) {
/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
spd = clk / (2 * (div + 2) + gsr);
if (spd <= speed)
break;
}
if (curr->speed == spd)
return 0;
writel(CR_I2CRST, &regs->cr);
mdelay(100);
if (readl(&regs->cr) & CR_I2CRST) {
printf("fti2c010: reset timeout\n");
return -1;
}
curr->speed = spd;
writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
writel(CDR_DIV(div), &regs->cdr);
return 0;
}
/*
* i2c_get_bus_speed:
*
* Returns speed of currently active I2C bus in Hz
*/
uint i2c_get_bus_speed(void)
{
return curr->speed;
}

81
drivers/i2c/fti2c010.h Normal file
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@ -0,0 +1,81 @@
/*
* Faraday I2C Controller
*
* (C) Copyright 2010 Faraday Technology
* Dante Su <dantesu@faraday-tech.com>
*
* This file is released under the terms of GPL v2 and any later version.
* See the file COPYING in the root directory of the source tree for details.
*/
#ifndef __FTI2C010_H
#define __FTI2C010_H
/*
* FTI2C010 registers
*/
struct fti2c010_regs {
uint32_t cr; /* 0x00: control register */
uint32_t sr; /* 0x04: status register */
uint32_t cdr; /* 0x08: clock division register */
uint32_t dr; /* 0x0c: data register */
uint32_t sar; /* 0x10: slave address register */
uint32_t tgsr;/* 0x14: time & glitch suppression register */
uint32_t bmr; /* 0x18: bus monitor register */
uint32_t rsvd[5];
uint32_t revr;/* 0x30: revision register */
};
/*
* control register
*/
#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
#define CR_DRIRQ 0x200 /* rx interrupt (both) */
#define CR_DTIRQ 0x100 /* tx interrupt (both) */
#define CR_TBEN 0x80 /* tx enable (both) */
#define CR_NAK 0x40 /* NACK (both) */
#define CR_STOP 0x20 /* stop (master) */
#define CR_START 0x10 /* start (master) */
#define CR_GCEN 0x8 /* general call support (slave) */
#define CR_SCLEN 0x4 /* enable clock out (master) */
#define CR_I2CEN 0x2 /* enable I2C (both) */
#define CR_I2CRST 0x1 /* reset I2C (both) */
#define CR_ENABLE \
(CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
/*
* status register
*/
#define SR_CLRAL 0x400 /* clear arbitration lost */
#define SR_CLRGC 0x200 /* clear general call */
#define SR_CLRSAM 0x100 /* clear slave address match */
#define SR_CLRSTOP 0x80 /* clear stop */
#define SR_CLRNAKR 0x40 /* clear NACK respond */
#define SR_DR 0x20 /* rx ready */
#define SR_DT 0x10 /* tx done */
#define SR_BB 0x8 /* bus busy */
#define SR_BUSY 0x4 /* chip busy */
#define SR_ACK 0x2 /* ACK/NACK received */
#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
/*
* clock division register
*/
#define CDR_DIV(n) ((n) & 0x3ffff)
/*
* time & glitch suppression register
*/
#define TGSR_GSR(n) (((n) & 0x7) << 10)
#define TGSR_TSR(n) ((n) & 0x3ff)
/*
* bus monitor register
*/
#define BMR_SCL 0x2 /* SCL is pull-up */
#define BMR_SDA 0x1 /* SDA is pull-up */
#endif /* __FTI2C010_H */