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mx5 clocks: Simplify imx_get_cspiclk()

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The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau
2012-09-27 10:23:42 +00:00
committed by Tom Rini
parent 08028b113e
commit 3cbd107b5f
1 changed files with 3 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm/cpu/armv7/mx5/clock.c
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@@ -378,32 +378,15 @@ static u32 get_uart_clk(void)
*/ */
static u32 imx_get_cspiclk(void) static u32 imx_get_cspiclk(void)
{ {
u32 ret_val = 0, pdf, pre_pdf, clk_sel; u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
u32 cscmr1 = readl(&mxc_ccm->cscmr1); u32 cscmr1 = readl(&mxc_ccm->cscmr1);
u32 cscdr2 = readl(&mxc_ccm->cscdr2); u32 cscdr2 = readl(&mxc_ccm->cscdr2);
pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2); pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2); pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1); clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
freq = get_standard_pll_sel_clk(clk_sel);
switch (clk_sel) { ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
break;
}
return ret_val; return ret_val;
} }