net: mvneta: Make driver 64bit safe

The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This
patch fixes the compilation warnings seen on this 64bit platform.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Stefan Roese 2016-05-19 18:09:17 +02:00
parent 3fda4ef395
commit 3cbc11da86

View File

@ -1022,7 +1022,7 @@ static int mvneta_txq_init(struct mvneta_port *pp,
txq->size = pp->tx_ring_size;
/* Allocate memory for TX descriptors */
txq->descs_phys = (u32)txq->descs;
txq->descs_phys = (dma_addr_t)txq->descs;
if (txq->descs == NULL)
return -ENOMEM;
@ -1504,10 +1504,10 @@ static int mvneta_send(struct udevice *dev, void *packet, int length)
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
tx_desc->buf_phys_addr = (u32)packet;
tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
tx_desc->data_size = length;
flush_dcache_range((u32)packet,
(u32)packet + ALIGN(length, PKTALIGN));
flush_dcache_range((ulong)packet,
(ulong)packet + ALIGN(length, PKTALIGN));
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
@ -1563,7 +1563,7 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
rx_bytes = rx_desc->data_size - 6;
/* give packet to stack - skip on first 2 bytes */
data = (u8 *)rx_desc->buf_cookie + 2;
data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
/*
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
@ -1594,13 +1594,13 @@ static int mvneta_probe(struct udevice *dev)
if (!buffer_loc.tx_descs) {
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE,
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
DCACHE_OFF);
buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
buffer_loc.rx_descs = (struct mvneta_rx_desc *)
((u32)bd_space +
((phys_addr_t)bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
buffer_loc.rx_buffers = (u32)
buffer_loc.rx_buffers = (phys_addr_t)
(bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));