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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2015-07-07 08:42:35 -04:00
commit 3cbb15d04f
15 changed files with 83 additions and 46 deletions
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2
arch/Kconfig
View File

@ -18,7 +18,7 @@ config ARC
config ARM
bool "ARM architecture"
select HAVE_PRIVATE_LIBGCC
select HAVE_PRIVATE_LIBGCC if !ARM64
select HAVE_GENERIC_BOARD
select SUPPORT_OF_CONTROL

7
arch/arm/cpu/armv7/start.S
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@ -22,10 +22,9 @@
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
* Do important init only if we don't start from memory!
* Setup memory and board specific bits prior to relocation.
* Relocate armboot to ram. Setup stack.
*
*************************************************************************/

4
arch/arm/include/asm/u-boot.h
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@ -49,8 +49,4 @@ typedef struct bd_info {
#define IH_ARCH_DEFAULT IH_ARCH_ARM64
#endif
#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD)
#error Thumb build does not work with private libgcc.
#endif
#endif /* _U_BOOT_H_ */

6
arch/arm/lib/_ashldi3.S
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@ -4,6 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#ifdef __ARMEB__
#define al r1
#define ah r0
@ -13,9 +15,8 @@
#endif
.globl __ashldi3
.globl __aeabi_llsl
__ashldi3:
__aeabi_llsl:
ENTRY(__aeabi_llsl)
subs r3, r2, #32
rsb ip, r2, #32
@ -24,3 +25,4 @@ __aeabi_llsl:
orrmi ah, ah, al, lsr ip
mov al, al, lsl r2
mov pc, lr
ENDPROC(__aeabi_llsl)

6
arch/arm/lib/_ashrdi3.S
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@ -4,6 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#ifdef __ARMEB__
#define al r1
#define ah r0
@ -13,9 +15,8 @@
#endif
.globl __ashrdi3
.globl __aeabi_lasr
__ashrdi3:
__aeabi_lasr:
ENTRY(__aeabi_lasr)
subs r3, r2, #32
rsb ip, r2, #32
@ -24,3 +25,4 @@ __aeabi_lasr:
orrmi al, al, ah, lsl ip
mov ah, ah, asr r2
mov pc, lr
ENDPROC(__aeabi_lasr)

6
arch/arm/lib/_divsi3.S
View File

@ -1,3 +1,5 @@
#include <linux/linkage.h>
.macro ARM_DIV_BODY dividend, divisor, result, curbit
#if __LINUX_ARM_ARCH__ >= 5
@ -95,9 +97,8 @@
.align 5
.globl __divsi3
.globl __aeabi_idiv
__divsi3:
__aeabi_idiv:
ENTRY(__aeabi_idiv)
cmp r1, #0
eor ip, r0, r1 @ save the sign of the result.
beq Ldiv0
@ -139,3 +140,4 @@ Ldiv0:
bl __div0
mov r0, #0 @ About as wrong as it could be.
ldr pc, [sp], #4
ENDPROC(__aeabi_idiv)

6
arch/arm/lib/_lshrdi3.S
View File

@ -4,6 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#ifdef __ARMEB__
#define al r1
#define ah r0
@ -13,9 +15,8 @@
#endif
.globl __lshrdi3
.globl __aeabi_llsr
__lshrdi3:
__aeabi_llsr:
ENTRY(__aeabi_llsr)
subs r3, r2, #32
rsb ip, r2, #32
@ -24,3 +25,4 @@ __aeabi_llsr:
orrmi al, al, ah, lsl ip
mov ah, ah, lsr r2
mov pc, lr
ENDPROC(__aeabi_llsr)

7
arch/arm/lib/_modsi3.S
View File

@ -1,3 +1,5 @@
#include <linux/linkage.h>
.macro ARM_MOD_BODY dividend, divisor, order, spare
#if __LINUX_ARM_ARCH__ >= 5
@ -69,8 +71,7 @@
.endm
.align 5
.globl __modsi3
__modsi3:
ENTRY(__modsi3)
cmp r1, #0
beq Ldiv0
rsbmi r1, r1, #0 @ loops below use unsigned.
@ -88,7 +89,7 @@ __modsi3:
10: cmp ip, #0
rsbmi r0, r0, #0
mov pc, lr
ENDPROC(__modsi3)
Ldiv0:

10
arch/arm/lib/_udivsi3.S
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@ -1,3 +1,5 @@
#include <linux/linkage.h>
/* # 1 "libgcc1.S" */
@ libgcc1 routines for ARM cpu.
@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@ -72,8 +74,7 @@ Ldiv0:
ldmia sp!, {pc}
.size __udivsi3 , . - __udivsi3
.globl __aeabi_uidivmod
__aeabi_uidivmod:
ENTRY(__aeabi_uidivmod)
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_uidiv
@ -81,9 +82,9 @@ __aeabi_uidivmod:
mul r3, r0, r2
sub r1, r1, r3
mov pc, lr
ENDPROC(__aeabi_uidivmod)
.globl __aeabi_idivmod
__aeabi_idivmod:
ENTRY(__aeabi_idivmod)
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_idiv
@ -91,3 +92,4 @@ __aeabi_idivmod:
mul r3, r0, r2
sub r1, r1, r3
mov pc, lr
ENDPROC(__aeabi_idivmod)

6
arch/arm/lib/_umodsi3.S
View File

@ -1,3 +1,5 @@
#include <linux/linkage.h>
/* # 1 "libgcc1.S" */
@ libgcc1 routines for ARM cpu.
@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
@ -11,10 +13,9 @@ curbit .req r3
/* lr .req r14 */
/* pc .req r15 */
.text
.globl __umodsi3
.type __umodsi3 ,function
.align 0
__umodsi3 :
ENTRY(__umodsi3)
cmp divisor, #0
beq Ldiv0
mov curbit, #1
@ -86,3 +87,4 @@ Ldiv0:
/* # 456 "libgcc1.S" */
/* # 500 "libgcc1.S" */
/* # 580 "libgcc1.S" */
ENDPROC(__umodsi3)

6
board/quipos/cairo/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
CAIRO BOARD
M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
S: Maintained
F: board/quipos/cairo/
F: include/configs/omap3_cairo.h
F: configs/cairo_defconfig

2
board/ti/am43xx/MAINTAINERS
View File

@ -5,3 +5,5 @@ F: board/ti/am43xx/
F: include/configs/am43xx_evm.h
F: configs/am43xx_evm_defconfig
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig

6
board/vscom/baltos/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
BALTOS BOARD
M: Yegor Yefremov <yegorslists@googlemail.com>
S: Maintained
F: board/vscom/baltos/
F: include/configs/baltos.h
F: configs/am335x_baltos_defconfig

39
drivers/gpio/lpc32xx_gpio.c
View File

@ -37,7 +37,7 @@
#define LPC32XX_GPIOS 128
struct lpc32xx_gpio_platdata {
struct lpc32xx_gpio_priv {
struct gpio_regs *regs;
/* GPIO FUNCTION: SEE WARNING #2 */
signed char function[LPC32XX_GPIOS];
@ -60,8 +60,8 @@ struct lpc32xx_gpio_platdata {
static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
int port, mask;
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct gpio_regs *regs = gpio_platdata->regs;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
@ -83,7 +83,7 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
}
/* GPIO FUNCTION: SEE WARNING #2 */
gpio_platdata->function[offset] = GPIOF_INPUT;
gpio_priv->function[offset] = GPIOF_INPUT;
return 0;
}
@ -95,8 +95,8 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
{
int port, rank, mask, value;
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct gpio_regs *regs = gpio_platdata->regs;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
@ -130,8 +130,8 @@ static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
static int gpio_set(struct udevice *dev, unsigned gpio)
{
int port, mask;
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct gpio_regs *regs = gpio_platdata->regs;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
@ -162,8 +162,8 @@ static int gpio_set(struct udevice *dev, unsigned gpio)
static int gpio_clr(struct udevice *dev, unsigned gpio)
{
int port, mask;
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct gpio_regs *regs = gpio_platdata->regs;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
@ -208,8 +208,8 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
int port, mask;
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct gpio_regs *regs = gpio_platdata->regs;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
@ -231,7 +231,7 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,
}
/* GPIO FUNCTION: SEE WARNING #2 */
gpio_platdata->function[offset] = GPIOF_OUTPUT;
gpio_priv->function[offset] = GPIOF_OUTPUT;
return lpc32xx_gpio_set_value(dev, offset, value);
}
@ -251,8 +251,8 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,
static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
return gpio_platdata->function[offset];
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
return gpio_priv->function[offset];
}
static const struct dm_gpio_ops gpio_lpc32xx_ops = {
@ -265,7 +265,7 @@ static const struct dm_gpio_ops gpio_lpc32xx_ops = {
static int lpc32xx_gpio_probe(struct udevice *dev)
{
struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
if (dev->of_offset == -1) {
@ -274,12 +274,11 @@ static int lpc32xx_gpio_probe(struct udevice *dev)
}
/* set base address for GPIO registers */
gpio_platdata->regs = (struct gpio_regs *)GPIO_BASE;
gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;
/* all GPIO functions are unknown until requested */
/* GPIO FUNCTION: SEE WARNING #2 */
memset(gpio_platdata->function, GPIOF_UNKNOWN,
sizeof(gpio_platdata->function));
memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function));
return 0;
}
@ -289,5 +288,5 @@ U_BOOT_DRIVER(gpio_lpc32xx) = {
.id = UCLASS_GPIO,
.ops = &gpio_lpc32xx_ops,
.probe = lpc32xx_gpio_probe,
.priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_platdata),
.priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv),
};

16
drivers/serial/arm_dcc.c
View File

@ -61,6 +61,22 @@
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
#elif defined(CONFIG_CPU_ARMV8)
/*
* ARMV8
*/
#define DCC_RBIT (1 << 30)
#define DCC_WBIT (1 << 29)
#define write_dcc(x) \
__asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
#define read_dcc(x) \
__asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
#define status_dcc(x) \
__asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
#else
#define DCC_RBIT (1 << 0)
#define DCC_WBIT (1 << 1)