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* Patch by Travis Sawyer, 09 Feb 2004:

Browse Source 
o 440GX:
    - Fix PCI Indirect access for type 1 config cycles with ppc440.
    - Add phymode for 440 enet
    - fix pci pre init
  o XPedite1K:
    - Change board_pre_init to board_early_init_f
    - Add user flash to bus controller setup
    - Fix pci pre init
    - Fix is_pci_host to check GPIO for monarch bit
    - Force xpedite1k to pci conventional mode (via #define option)

* Patch by Brad Kemp, 4 Feb 2004:
  - handle the machine check that is generated during the PCI scans
    on 82xx processors.
  - define the registers used in the IMMR by the PCI subsystem.

* Patch by Pierre Aubert, 03 Feb 2004:
  cpu/mpc5xxx/start.S: copy MBAR into SPR311

* Patch by Jeff Angielski, 03 Feb 2004:
  Fix copy & paste error in cpu/mpc8260/pci.c

* Patch by Reinhard Meyer, 24 Jan 2004:
  Fix typo in cpu/mpc5xxx/pci_mpc5200.c
This commit is contained in:
wdenk 2004-02-22 23:46:08 +00:00
parent cf56e11019
commit 3c74e32a98
17 changed files with 963 additions and 743 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
CHANGELOG
View File

@ -2,6 +2,32 @@
Changes for U-Boot 1.0.2:
======================================================================
* Patch by Travis Sawyer, 09 Feb 2004:
o 440GX:
- Fix PCI Indirect access for type 1 config cycles with ppc440.
- Add phymode for 440 enet
- fix pci pre init
o XPedite1K:
- Change board_pre_init to board_early_init_f
- Add user flash to bus controller setup
- Fix pci pre init
- Fix is_pci_host to check GPIO for monarch bit
- Force xpedite1k to pci conventional mode (via #define option)
* Patch by Brad Kemp, 4 Feb 2004:
- handle the machine check that is generated during the PCI scans
on 82xx processors.
- define the registers used in the IMMR by the PCI subsystem.
* Patch by Pierre Aubert, 03 Feb 2004:
cpu/mpc5xxx/start.S: copy MBAR into SPR311
* Patch by Jeff Angielski, 03 Feb 2004:
Fix copy & paste error in cpu/mpc8260/pci.c
* Patch by Reinhard Meyer, 24 Jan 2004:
Fix typo in cpu/mpc5xxx/pci_mpc5200.c
* Add Auto-MDIX support for INCA-IP
* Some code cleanup

4
board/xpedite1k/config.mk
View File

@ -22,11 +22,9 @@
#
#
# esd ADCIOP boards
# XES XPedite1000 PPC440GX
#
#TEXT_BASE = 0xFFFE0000
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else

27
board/xpedite1k/xpedite1k.c
View File

@ -32,7 +32,7 @@
long int fixed_sdram (void);
int board_pre_init (void)
int board_early_init_f(void)
{
unsigned long sdrreg;
/* TBS: Setup the GPIO access for the user LEDs */
@ -51,6 +51,8 @@ int board_pre_init (void)
/* set the bus controller */
mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */
mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */
mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@ -217,17 +219,18 @@ long int fixed_sdram (void)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* TBS:
* The xpedite1k is a PrPMC board, however for our purposes it is the host
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00100000) == 0 ){
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
/* See if we're supposed to setup the pci */
mfsdr(sdr_sdstp1, strap);
if ((strap & 0x00010000) == 0) {
return (0);
}
#if defined(CFG_PCI_FORCE_PCI_CONV)
/* Setup System Device Register PCIX0_XCR */
mfsdr(sdr_xcr, strap);
strap &= 0x0f000000;
mtsdr(sdr_xcr, strap);
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
@ -292,9 +295,7 @@ void pci_target_init(struct pci_controller * hose )
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ebony board is always configured as host. */
/* TBS: The xpedite1k is not necessarily the host, however for our purposes, it is. */
return(1);
return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0);
}
#endif /* defined(CONFIG_PCI) */

2
cpu/mpc5xxx/pci_mpc5200.c
View File

@ -115,7 +115,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
/* Map MBAR to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
*(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);

2
cpu/mpc5xxx/start.S
View File

@ -145,6 +145,8 @@ lowboot_reentry:
lis r3, CFG_MBAR@h
ori r3, r3, CFG_MBAR@l
#if defined(CONFIG_MPC5200)
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
rlwinm r3, r3, 16, 16, 31
#endif
#if defined(CONFIG_MGT5100)

349
cpu/mpc8260/pci.c
View File

@ -28,28 +28,28 @@
#include <pci.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <asm/io.h>
/*
* Local->PCI map (from CPU) controlled by
* Local->PCI map (from CPU) controlled by
* MPC826x master window
*
* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
*
* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
* PCI Mem with prefetch
* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
* PCI Mem with prefetch
*
* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
* PCI Mem w/o prefetch
* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
* PCI Mem w/o prefetch
*
* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
* 32-bit PCI IO
* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
* 32-bit PCI IO
*
* PCI->Local map (from PCI)
* MPC826x slave window controlled by
* MPC826x slave window controlled by
*
* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
* MPC826x local memory
* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
* MPC826x local memory
*/
/*
@ -58,13 +58,13 @@
*/
#ifndef CFG_PCI_SLV_MEM_LOCAL
#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
#else
#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
#endif
#ifndef CFG_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
#else
#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
#endif
@ -85,28 +85,28 @@
/* PCIBR0 */
#ifndef CFG_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
#else
#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
#endif
#ifndef CFG_PCIMSK0_MASK
#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
#else
#define PCIMSK0_MASK CFG_PCIMSK0_MASK
#endif
/* PCIBR1 */
#ifndef CFG_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
#else
#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
#endif
#ifndef CFG_PCIMSK1_MASK
#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
#else
#define PCIMSK1_MASK CFG_PCIMSK1_MASK
#define PCIMSK1_MASK CFG_PCIMSK1_MASK
#endif
/*
@ -116,13 +116,13 @@
*/
#ifndef CFG_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#else
#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
#endif
#ifndef CFG_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#else
#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
#endif
@ -134,7 +134,7 @@
#endif
#ifndef CFG_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
#else
#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
#endif
@ -152,13 +152,13 @@
*/
#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#else
#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
#endif
#ifndef CFG_PCI_MSTR_MEMIO_BUS
#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
#else
#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
#endif
@ -170,13 +170,13 @@
#endif
#ifndef CFG_PCI_MSTR_MEMIO_SIZE
#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
#else
#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
#endif
#ifndef CFG_POCMR1_MASK_ATTRIB
#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
#else
#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
#endif
@ -188,13 +188,13 @@
*/
#ifndef CFG_PCI_MSTR_IO_LOCAL
#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
#else
#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
#endif
#ifndef CFG_PCI_MSTR_IO_BUS
#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
#else
#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
#endif
@ -206,13 +206,13 @@
#endif
#ifndef CFG_PCI_MSTR_IO_SIZE
#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
#else
#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
#endif
#ifndef CFG_POCMR2_MASK_ATTRIB
#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#else
#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
#endif
@ -223,193 +223,198 @@
#define PCI_CLASS_BRIDGE_CTLR 0x06
static inline void pci_outl(u32 addr, u32 data)
static inline void pci_outl (u32 addr, u32 data)
{
*(volatile u32 *) addr = cpu_to_le32(data);
*(volatile u32 *) addr = cpu_to_le32 (data);
}
void pci_mpc8250_init(struct pci_controller *hose)
void pci_mpc8250_init (struct pci_controller *hose)
{
#ifdef CONFIG_MPC8266ADS
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
#endif
u16 tempShort;
u32 immr_addr = CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
pci_dev_t host_devno = PCI_BDF(0, 0, 0);
u16 tempShort;
pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
CFG_IMMR + PCI_CFG_DATA_REG);
volatile immap_t *immap = (immap_t *) CFG_IMMR;
pci_dev_t host_devno = PCI_BDF (0, 0, 0);
/*
* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
*/
pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
CFG_IMMR + PCI_CFG_DATA_REG);
/*
* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
*/
#ifdef CONFIG_MPC8266ADS
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
* and local bus for PCI (SIUMCR [LBPC]).
*/
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_LBPC11 &
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
* and local bus for PCI (SIUMCR [LBPC]).
*/
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_LBPC11 &
~SIUMCR_CS10PC11 &
~SIUMCR_LBPC11) |
SIUMCR_LBPC01 |
SIUMCR_CS10PC01 |
SIUMCR_LBPC01;
~SIUMCR_LBPC11) |
SIUMCR_LBPC01 |
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#endif
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits
is highest priority */
/* Bus 4bit value
--- ----------
CPM high 0b0000
CPM middle 0b0001
CPM low 0b0010
PCI reguest 0b0011
Reserved 0b0100
Reserved 0b0101
Internal Core 0b0110
External Master 1 0b0111
External Master 2 0b1000
External Master 3 0b1001
The rest are reserved */
immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits
is highest priority */
/* Bus 4bit value
--- ----------
CPM high 0b0000
CPM middle 0b0001
CPM low 0b0010
PCI reguest 0b0011
Reserved 0b0100
Reserved 0b0101
Internal Core 0b0110
External Master 1 0b0111
External Master 2 0b1000
External Master 3 0b1001
The rest are reserved */
immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
/* Park bus on core while modifying PCI Bus accesses */
immap->im_siu_conf.sc_ppc_acr = 0x6;
/* Park bus on core while modifying PCI Bus accesses */
immap->im_siu_conf.sc_ppc_acr = 0x6;
/*
* Set up master windows that allow the CPU to access PCI space. These
* windows are set up using the two SIU PCIBR registers.
*/
*(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
*(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
PCI_MSTR0_LOCAL | PCIBR_ENABLE;
/*
* Set up master windows that allow the CPU to access PCI space. These
* windows are set up using the two SIU PCIBR registers.
*/
immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
#ifdef CONFIG_MPC8266ADS
*(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
*(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
PCI_MSTR1_LOCAL | PCIBR_ENABLE;
immap->im_memctl.memc_pcimsk0 = PCIMSK1_MASK;
immap->im_memctl.memc_pcibr0 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif
/* Release PCI RST (by default the PCI RST signal is held low) */
pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
/* Release PCI RST (by default the PCI RST signal is held low) */
immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
/* give it some time */
{
/* give it some time */
{
#ifdef CONFIG_MPC8266ADS
/* Give the PCI cards more time to initialize before query
This might be good for other boards also
*/
int i;
for (i = 0; i < 1000; ++i)
This might be good for other boards also
*/
int i;
for (i = 0; i < 1000; ++i)
#endif
udelay(1000);
}
udelay (1000);
}
/*
* Set up master window that allows the CPU to access PCI Memory (prefetch)
* space. This window is set up using the first set of Outbound ATU registers.
*/
pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */
pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */
/*
* Set up master window that allows the CPU to access PCI Memory (prefetch)
* space. This window is set up using the first set of Outbound ATU registers.
*/
immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
/*
* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
* space. This window is set up using the second set of Outbound ATU registers.
*/
pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */
/*
* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
* space. This window is set up using the second set of Outbound ATU registers.
*/
immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
/*
* Set up master window that allows the CPU to access PCI IO space. This window
* is set up using the third set of Outbound ATU registers.
*/
pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12); /* PCI base */
pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */
/*
* Set up master window that allows the CPU to access PCI IO space. This window
* is set up using the third set of Outbound ATU registers.
*/
immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
/*
* Set up slave window that allows PCI masters to access MPC826x local memory.
* This window is set up using the first set of Inbound ATU registers
*/
pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12); /* PCI base */
pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB); /* Size & attribute */
/*
* Set up slave window that allows PCI masters to access MPC826x local memory.
* This window is set up using the first set of Inbound ATU registers
*/
immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
/* See above for description - puts PCI request as highest priority */
immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
/* See above for description - puts PCI request as highest priority */
immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
/* Park the bus on the PCI */
immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
/* Park the bus on the PCI */
immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
/* Host mode - specify the bridge as a host-PCI bridge */
/* Host mode - specify the bridge as a host-PCI bridge */
pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
PCI_CLASS_BRIDGE_CTLR);
pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
PCI_CLASS_BRIDGE_CTLR);
/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
tempShort | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
#ifdef CONFIG_MPC8266ADS
/* do some bridge init, should be done on all 8260 based bridges */
pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
#endif
pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
0x08);
pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
0xF8);
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System memory space */
/* System memory space */
#ifdef CONFIG_MPC8266ADS
pci_set_region(hose->regions + 0,
PCI_SLV_MEM_BUS,
PCI_SLV_MEM_LOCAL,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_MEMORY);
pci_set_region (hose->regions + 0,
PCI_SLV_MEM_BUS,
PCI_SLV_MEM_LOCAL,
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
#else
pci_set_region(hose->regions + 0,
CFG_SDRAM_BASE,
CFG_SDRAM_BASE,
0x4000000,
PCI_REGION_MEM | PCI_REGION_MEMORY);
pci_set_region (hose->regions + 0,
CFG_SDRAM_BASE,
CFG_SDRAM_BASE,
0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
#endif
/* PCI memory space */
/* PCI memory space */
#ifdef CONFIG_MPC8266ADS
pci_set_region(hose->regions + 1,
PCI_MSTR_MEMIO_BUS,
PCI_MSTR_MEMIO_LOCAL,
PCI_MSTR_MEMIO_SIZE,
PCI_REGION_MEM);
pci_set_region (hose->regions + 1,
PCI_MSTR_MEMIO_BUS,
PCI_MSTR_MEMIO_LOCAL,
PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
#else
pci_set_region(hose->regions + 1,
PCI_MSTR_MEM_BUS,
PCI_MSTR_MEM_LOCAL,
PCI_MSTR_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region (hose->regions + 1,
PCI_MSTR_MEM_BUS,
PCI_MSTR_MEM_LOCAL,
PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
#endif
/* PCI I/O space */
pci_set_region(hose->regions + 2,
PCI_MSTR_IO_BUS,
PCI_MSTR_IO_LOCAL,
PCI_MSTR_IO_SIZE,
PCI_REGION_IO);
/* PCI I/O space */
pci_set_region (hose->regions + 2,
PCI_MSTR_IO_BUS,
PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = 3;
pci_register_hose(hose);
pci_register_hose (hose);
/* Mask off master abort machine checks */
immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
eieio ();
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = pci_hose_scan (hose);
/* clear the error in the error status register */
immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
/* unmask master abort machine checks */
immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
}
#endif /* CONFIG_PCI */
#endif /* CONFIG_PCI */

42
cpu/mpc8260/traps.c
View File

@ -35,6 +35,7 @@
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/m8260_pci.h>
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
@ -86,14 +87,12 @@ void show_regs(struct pt_regs * regs)
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
if ((i % 8) == 0) {
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
if ((i % 8) == 7) {
printf("\n");
}
}
@ -108,6 +107,24 @@ _exception(int signr, struct pt_regs *regs)
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
#ifdef CONFIG_PCI
void dump_pci (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
printf ("PCI: err status %x err mask %x err ctrl %x\n",
le32_to_cpu (immap->im_pci.pci_esr),
le32_to_cpu (immap->im_pci.pci_emr),
le32_to_cpu (immap->im_pci.pci_ecr));
printf (" error address %x error data %x ctrl %x\n",
le32_to_cpu (immap->im_pci.pci_eacr),
le32_to_cpu (immap->im_pci.pci_edcr),
le32_to_cpu (immap->im_pci.pci_eccr));
}
#endif
void
MachineCheckException(struct pt_regs *regs)
{
@ -117,6 +134,17 @@ MachineCheckException(struct pt_regs *regs)
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
#ifdef CONFIG_PCI
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#ifdef DEBUG
dump_pci();
#endif
/* clear the error in the error status register */
if(immap->im_pci.pci_esr && cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
return;
}
#endif
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
return;
@ -130,8 +158,7 @@ MachineCheckException(struct pt_regs *regs)
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ",regs);
switch( regs->msr & 0x0000F000)
{
switch( regs->msr & 0x0000F000) {
case (1<<12) :
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
@ -150,6 +177,9 @@ MachineCheckException(struct pt_regs *regs)
}
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
#ifdef CONFIG_PCI
dump_pci();
#endif
panic("machine check");
}

33
cpu/ppc4xx/405gp_pci.c
View File

@ -411,15 +411,23 @@ void pci_440_init (struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00040000) == 0 ){
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#if defined (CONFIG_440_GX)
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#else
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00040000) == 0 ){
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
/*--------------------------------------------------------------------------+
* PCI controller init
*--------------------------------------------------------------------------*/
@ -463,8 +471,13 @@ void pci_440_init (struct pci_controller *hose)
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
#if defined(CONFIG_440_GX)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#else
out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
#endif
/*--------------------------------------------------------------------------+
* PCI master init: default is one 256MB region for PCI memory:

46
cpu/ppc4xx/440gx_enet.c
View File

@ -116,6 +116,10 @@
#undef INFO_440_ENET
#define BI_PHYMODE_NONE 0
#define BI_PHYMODE_ZMII 1
#define BI_PHYMODE_RGMII 2
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
@ -316,11 +320,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
break;
}
bis->bi_phynum[devnum] = reg;
/* Reset the phy */
miiphy_reset (reg);
/* Start/Restart autonegotiation */
/* miiphy_write(reg, PHY_BMCR, 0x9340); */
phy_setup_aneg (reg);
udelay (1000);
@ -579,13 +584,6 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
#if 0 /* done by irq_install_handler */
/* set up interrupt handler */
/* setup interrupt controller to take interrupts from the MAL &
EMAC */
mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
#endif
mtmsr (msr); /* enable interrupts again */
@ -1027,33 +1025,49 @@ int ppc_440x_eth_initialize (bd_t * bis)
pfc1 &= ~(0x01e00000);
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
bis->bi_phymode[1] = 0;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
case 0:
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
case 1:
if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) ==
0)
if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
case 2:
if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) ==
0)
if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
case 3:
if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) ==
0)
if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
default:
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
}

4
drivers/inca-ip_sw.c
View File

@ -69,7 +69,7 @@
/************************ Auto MDIX settings ************************/
#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
@ -173,7 +173,7 @@ int inca_switch_initialize(bd_t * bis)
inca_dma_init();
inca_init_switch_chip();
inca_amdix();
sprintf(dev->name, "INCA-IP Switch");

68
drivers/pci_auto.c
View File

@ -46,16 +46,14 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned
{
unsigned long addr;
if (!res)
{
if (!res) {
DEBUGF("No resource");
goto error;
}
addr = ((res->bus_lower - 1) | (size - 1)) + 1;
if (addr - res->bus_start + size > res->size)
{
if (addr - res->bus_start + size > res->size) {
DEBUGF("No room in resource");
goto error;
}
@ -90,8 +88,7 @@ void pciauto_setup_device(struct pci_controller *hose,
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
{
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
@ -103,15 +100,12 @@ void pciauto_setup_device(struct pci_controller *hose,
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE)
{
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
}
else
{
} else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
@ -122,8 +116,7 @@ void pciauto_setup_device(struct pci_controller *hose,
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
}
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
{
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, bar_value);
@ -132,8 +125,7 @@ void pciauto_setup_device(struct pci_controller *hose,
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
if (found_mem64)
{
if (found_mem64) {
bar += 4;
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
}
@ -163,12 +155,10 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
/* TBS: passed in sub_bus is correct, removed the +1 */
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem)
{
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
@ -179,8 +169,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
cmdstat |= PCI_COMMAND_MEMORY;
}
if (pci_io)
{
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
@ -209,8 +198,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
if (pci_mem)
{
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
@ -218,8 +206,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
(pci_mem->bus_lower-1) >> 16);
}
if (pci_io)
{
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
@ -240,10 +227,8 @@ void pciauto_config_init(struct pci_controller *hose)
hose->pci_io = hose->pci_mem = NULL;
for (i=0; i<hose->region_count; i++)
{
switch(hose->regions[i].flags)
{
for (i=0; i<hose->region_count; i++) {
switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
hose->pci_io->size < hose->regions[i].size)
@ -258,8 +243,7 @@ void pciauto_config_init(struct pci_controller *hose)
}
if (hose->pci_mem)
{
if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
@ -267,8 +251,7 @@ void pciauto_config_init(struct pci_controller *hose)
hose->pci_mem->bus_start + hose->pci_mem->size - 1);
}
if (hose->pci_io)
{
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
@ -289,23 +272,22 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
switch(class)
{
switch(class) {
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
/* TBS: Passing in current_busno allows for sibling P2P bridges */
/* Passing in current_busno allows for sibling P2P bridges */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
/*
* TBS: need to figure out if this is a subordinate bridge on the bus
* need to figure out if this is a subordinate bridge on the bus
* to be able to properly set the pri/sec/sub bridge registers.
*/
n = pci_hose_scan_bus(hose, hose->current_busno);
/* TBS: figure out the deepest we've gone for this leg */
/* figure out the deepest we've gone for this leg */
sub_bus = max(n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
@ -314,11 +296,10 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
case PCI_CLASS_STORAGE_IDE:
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
{
DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
return sub_bus;
}
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
return sub_bus;
}
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
break;
@ -327,8 +308,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
/* just do a minimal setup of the bridge, let the OS take care of the rest */
pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
hose->current_busno++;
break;

13
drivers/pci_indirect.c
View File

@ -43,6 +43,19 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440_GX)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
if (PCI_BUS(dev) > 0) \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
else \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \

144
include/asm-ppc/immap_8260.h
View File

@ -1,18 +1,17 @@
/*
* MPC8260 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* The Internal Memory Map of the 8260. I don't know how generic
* The Internal Memory Map of the 8260. I don't know how generic
* this will be, as I don't have any knowledge of the subsequent
* parts at this time. I copied this from the 8xx_immap.h.
* parts at this time. I copied this from the 8xx_immap.h.
*/
#ifndef __IMMAP_82XX__
#define __IMMAP_82XX__
/* System configuration registers.
*/
typedef struct sys_conf {
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
char res1[6];
@ -89,7 +88,12 @@ typedef struct mem_ctlr {
u_char memc_lsrt;
char res9[3];
uint memc_immr;
char res10[84];
uint memc_pcibr0;
uint memc_pcibr1;
char res10[16];
uint memc_pcimsk0;
uint memc_pcimsk1;
char res11[52];
} memctl8260_t;
/* System Integration Timers.
@ -107,9 +111,136 @@ typedef struct sys_int_timers {
uint sit_pitc;
uint sit_pitr;
char res6[94];
char res7[2390];
char res7[390];
} sit8260_t;
/* PCI
*/
typedef struct pci_config {
uint pci_omisr;
uint pci_ominr;
char res1[8];
uint pci_ifqpr;
uint pci_ofqpr;
char res2[8];
uint pci_imr0;
uint pci_imr1;
uint pci_omr0;
uint pci_omr1;
uint pci_odr;
char res3[4];
uint pci_idr;
char res4[20];
uint pci_imisr;
uint pci_imimr;
char res5[24];
uint pci_ifhpr;
uint pci_iftpr;
char res6[8];
uint pci_iphpr;
uint pci_iptpr;
char res7[8];
uint pci_ofhpr;
uint pci_oftpr;
char res8[8];
uint pci_ophpr;
uint pci_optpr;
char res9[12];
uint pci_mucr;
char res10[8];
uint pci_qbar;
char res11[12];
uint pci_dmamr0;
uint pci_dmasr0;
uint pci_dmacdar0;
char res12[4];
uint pci_dmasar0;
char res13[4];
uint pci_dmadar0;
char res14[4];
uint pci_dmabcr0;
uint pci_dmandar0;
char res15[88];
uint pci_dmamr1;
uint pci_dmasr1;
uint pci_dmacdar1;
char res16[4];
uint pci_dmasar1;
char res17[4];
uint pci_dmadar1;
char res18[4];
uint pci_dmabcr1;
uint pci_dmandar1;
char res19[88];
uint pci_dmamr2;
uint pci_dmasr2;
uint pci_dmacdar2;
char res20[4];
uint pci_dmasar2;
char res21[4];
uint pci_dmadar2;
char res22[4];
uint pci_dmabcr2;
uint pci_dmandar2;
char res23[88];
uint pci_dmamr3;
uint pci_dmasr3;
uint pci_dmacdar3;
char res24[4];
uint pci_dmasar3;
char res25[4];
uint pci_dmadar3;
char res26[4];
uint pci_dmabcr3;
uint pci_dmandar3;
char res27[344];
uint pci_potar0;
char res28[4];
uint pci_pobar0;
char res29[4];
uint pci_pocmr0;
char res30[4];
uint pci_potar1;
char res31[4];
uint pci_pobar1;
char res32[4];
uint pci_pocmr1;
char res33[4];
uint pci_potar2;
char res34[4];
uint pci_pobar2;
char res35[4];
uint pci_pocmr2;
char res36[52];
uint pci_ptcr;
uint pci_gpcr;
uint pci_gcr;
uint pci_esr;
uint pci_emr;
uint pci_ecr;
uint pci_eacr;
char res37[4];
uint pci_edcr;
char res38[4];
uint pci_eccr;
char res39[44];
uint pci_pitar1;
char res40[4];
uint pci_pibar1;
char res41[4];
uint pci_picmr1;
char res42[4];
uint pci_pitar0;
char res43[4];
uint pci_pibar0;
char res44[4];
uint pci_picmr0;
char res45[4];
uint pci_cfg_addr;
uint pci_cfg_data;
uint pci_int_ack;
char res46[756];
}pci8260_t;
#define PISCR_PIRQ_MASK ((ushort)0xff00)
#define PISCR_PS ((ushort)0x0080)
#define PISCR_PIE ((ushort)0x0004)
@ -375,6 +506,7 @@ typedef struct immap {
sysconf8260_t im_siu_conf; /* SIU Configuration */
memctl8260_t im_memctl; /* Memory Controller */
sit8260_t im_sit; /* System Integration Timers */
pci8260_t im_pci; /* PCI Configuration */
intctl8260_t im_intctl; /* Interrupt Controller */
car8260_t im_clkrst; /* Clocks and reset */
iop8260_t im_ioport; /* IO Port control/status */

936
include/asm-ppc/processor.h
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File diff suppressed because it is too large Load Diff

4
include/asm-ppc/u-boot.h
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@ -104,6 +104,10 @@ typedef struct bd_info {
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
#if defined(CONFIG_440_GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
#endif
} bd_t;
#endif /* __ASSEMBLY__ */

2
include/bmp_logo.h
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@ -18,7 +18,7 @@ unsigned short bmp_logo_palette[] = {
0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999,
0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3,
0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA,
0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
};
unsigned char bmp_logo_bitmap[] = {

4
include/configs/XPEDITE1K.h
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@ -37,7 +37,7 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440_GX 1 /* 440 GX */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@ -235,7 +235,7 @@ extern void out32(unsigned int, unsigned long);
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is