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imx8m: add sdhc/nand/ecspi clk api

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Current DM CLK is a bit complicated, for simplity, let DM clk only
support enable/disable/get_rate. For the expected rate settings,
we use non-DM clk to do that. Then we could have simple DM clk for
i.MX and could also share between SPL/U-Boot proper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-07-09 11:35:15 +08:00
parent 14254e646d
commit 3c1c28d4e0
1 changed files with 66 additions and 0 deletions
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66
arch/arm/mach-imx/imx8m/clock_imx8mm.c
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@ -317,6 +317,72 @@ void init_wdog_clk(void)
clock_enable(CCGR_WDOG3, 1);
}
void init_clk_usdhc(u32 index)
{
/*
* set usdhc clock root
* sys pll1 400M
*/
switch (index) {
case 0:
clock_enable(CCGR_USDHC1, 0);
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USDHC1, 1);
return;
case 1:
clock_enable(CCGR_USDHC2, 0);
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USDHC2, 1);
return;
case 2:
clock_enable(CCGR_USDHC3, 0);
clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USDHC3, 1);
return;
default:
printf("Invalid usdhc index\n");
return;
}
}
void init_clk_ecspi(u32 index)
{
switch (index) {
case 0:
clock_enable(CCGR_ECSPI1, 0);
clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI1, 1);
return;
case 1:
clock_enable(CCGR_ECSPI2, 0);
clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI2, 1);
case 2:
clock_enable(CCGR_ECSPI3, 0);
clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI3, 1);
return;
default:
printf("Invalid ecspi index\n");
return;
}
}
void init_nand_clk(void)
{
/*
* set rawnand root
* sys pll1 400M
*/
clock_enable(CCGR_RAWNAND, 0);
clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
clock_enable(CCGR_RAWNAND, 1);
}
int clock_init(void)
{
u32 val_cfg0;