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imx: imx7d-sdb: Add DM QSPI support

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On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.

Other changes to support the DM QSPI:
 - Add QSPI node and alias spi0.
 - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
   conflict
 - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
   align with kernel and also present the conflict.
 - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
   "spi-flash"
 - Remove iomux settings of qspi in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
2018-06-27 19:30:53 -07:00
committed by Stefano Babic
parent 0925ee2185
commit 3b82335015
9 changed files with 175 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
View File

@@ -445,7 +445,8 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb.dtb
imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb

10
arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
&qspi1 {
flash0: mx25l51245g@0 {
compatible = "spi-flash";
};
};

44
arch/arm/dts/imx7d-sdb-qspi.dts Normal file
View File

@@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*/
#include "imx7d-sdb.dts"
/* disable epdc, conflict with qspi */
&epdc {
status = "disabled";
};
&iomuxc {
qspi1 {
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
>;
};
};
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
status = "okay";
ddrsmp=<0>;
flash0: mx25l51245g@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l51245g";
spi-max-frequency = <29000000>;
/* take off one dummy cycle */
spi-nor,ddr-quad-read-dummy = <5>;
reg = <0>;
};
};

6
arch/arm/dts/imx7d-sdb.dts
View File

@@ -11,11 +11,15 @@
model = "Freescale i.MX7 SabreSD Board";
compatible = "fsl,imx7d-sdb", "fsl,imx7d";
aliases {
spi5 = &soft_spi;
};
memory {
reg = <0x80000000 0x80000000>;
};
spi4 {
soft_spi: soft-spi {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;

12
arch/arm/dts/imx7d.dtsi
View File

@@ -86,6 +86,18 @@
};
};
&aips2 {
epdc: epdc@306f0000 {
compatible = "fsl,imx7d-epdc";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x306f0000 0x10000>;
clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
clock-names = "epdc_axi", "epdc_pix";
epdc-ram = <&gpr 0x4 30>;
status = "disabled";
};
};
&aips3 {
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";

22
arch/arm/dts/imx7s.dtsi
View File

@@ -82,10 +82,11 @@
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
spi0 = &qspi1;
spi1 = &ecspi1;
spi2 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
};
cpus {
@@ -1072,6 +1073,19 @@
status = "disabled";
};
qspi1: qspi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-qspi";
reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
<&clks IMX7D_QSPI_ROOT_CLK>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;