Merge branch '2021-04-11-remove-non-migrated-boards'
- Remove a large number of boards that have not migrated to DM_MMC, for which the migration deadline with 2 years ago at v2019.04.
This commit is contained in:
Tom Rini
@@ -346,7 +346,7 @@ config SYS_CACHELINE_SIZE
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choice
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prompt "Select the ARM data write cache policy"
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default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
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TARGET_BCMNSP || CPU_PXA || RZA1
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CPU_PXA || RZA1
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default SYS_ARM_CACHE_WRITEBACK
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config SYS_ARM_CACHE_WRITEBACK
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@@ -561,11 +561,6 @@ config ARCH_MVEBU
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select SPI
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imply CMD_DM
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config TARGET_APF27
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bool "Support apf27"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config ARCH_ORION5X
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bool "Marvell Orion"
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select CPU_ARM926EJS
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@@ -650,13 +645,6 @@ config ARCH_BCM6858
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select OF_CONTROL
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imply CMD_DM
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config TARGET_VEXPRESS_CA15_TC2
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bool "Support vexpress_ca15_tc2"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select PL011_SERIAL
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config ARCH_BCMSTB
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bool "Broadcom BCM7XXX family"
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select CPU_V7A
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@@ -668,28 +656,6 @@ config ARCH_BCMSTB
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This enables support for Broadcom ARM-based set-top box
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chipsets, including the 7445 family of chips.
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config TARGET_VEXPRESS_CA5X2
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bool "Support vexpress_ca5x2"
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select CPU_V7A
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select PL011_SERIAL
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config TARGET_VEXPRESS_CA9X4
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bool "Support vexpress_ca9x4"
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select CPU_V7A
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select PL011_SERIAL
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config TARGET_BCM23550_W1D
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bool "Support bcm23550_w1d"
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select CPU_V7A
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imply CRC32_VERIFY
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imply FAT_WRITE
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config TARGET_BCM28155_AP
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bool "Support bcm28155_ap"
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select CPU_V7A
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imply CRC32_VERIFY
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imply FAT_WRITE
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config TARGET_BCMCYGNUS
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bool "Support bcmcygnus"
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select CPU_V7A
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@@ -701,10 +667,6 @@ config TARGET_BCMCYGNUS
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imply HASH_VERIFY
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imply NETDEVICES
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config TARGET_BCMNSP
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bool "Support bcmnsp"
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select CPU_V7A
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config TARGET_BCMNS2
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bool "Support Broadcom Northstar2"
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select ARM64
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@@ -954,11 +916,6 @@ config ARCH_RMOBILE
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imply SYS_THUMB_BUILD
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imply ARCH_MISC_INIT if DISPLAY_CPUINFO
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config TARGET_S32V234EVB
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bool "Support s32v234evb"
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select ARM64
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select SYS_FSL_ERRATUM_ESDHC111
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config ARCH_SNAPDRAGON
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bool "Qualcomm Snapdragon SoCs"
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select ARM64
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@@ -1969,18 +1926,11 @@ source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/gplugd/Kconfig"
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source "board/Marvell/octeontx/Kconfig"
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source "board/Marvell/octeontx2/Kconfig"
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source "board/armadeus/apf27/Kconfig"
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source "board/armltd/vexpress/Kconfig"
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source "board/armltd/vexpress64/Kconfig"
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source "board/cortina/presidio-asic/Kconfig"
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source "board/broadcom/bcm23550_w1d/Kconfig"
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source "board/broadcom/bcm28155_ap/Kconfig"
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source "board/broadcom/bcm963158/Kconfig"
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source "board/broadcom/bcm968360bg/Kconfig"
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source "board/broadcom/bcm968580xref/Kconfig"
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source "board/broadcom/bcmcygnus/Kconfig"
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source "board/broadcom/bcmnsp/Kconfig"
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source "board/broadcom/bcmns2/Kconfig"
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source "board/broadcom/bcmns3/Kconfig"
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source "board/cavium/thunderx/Kconfig"
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source "board/cirrus/edb93xx/Kconfig"
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@@ -2003,7 +1953,6 @@ source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/ls1012afrdm/Kconfig"
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source "board/freescale/lx2160a/Kconfig"
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source "board/freescale/s32v234evb/Kconfig"
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source "board/grinn/chiliboard/Kconfig"
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source "board/hisilicon/hikey/Kconfig"
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source "board/hisilicon/hikey960/Kconfig"
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@@ -116,7 +116,7 @@ config PSCI_RESET
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!TARGET_LS1046AFRWY && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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!ARCH_UNIPHIER
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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ARM Trusted Firmware or other firmware.
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@@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
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obj-y += generic.o
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obj-y += cpu.o
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@@ -1,102 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch/mc_me_regs.h>
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#include <linux/bitops.h>
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#include "cpu.h"
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u32 cpu_mask(void)
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{
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return readl(MC_ME_CS);
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#define S32V234_IRAM_BASE 0x3e800000UL
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#define S32V234_IRAM_SIZE 0x800000UL
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#define S32V234_DRAM_BASE1 0x80000000UL
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#define S32V234_DRAM_SIZE1 0x40000000UL
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#define S32V234_DRAM_BASE2 0xC0000000UL
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#define S32V234_DRAM_SIZE2 0x20000000UL
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#define S32V234_PERIPH_BASE 0x40000000UL
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#define S32V234_PERIPH_SIZE 0x40000000UL
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static struct mm_region s32v234_mem_map[] = {
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{
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.virt = S32V234_IRAM_BASE,
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.phys = S32V234_IRAM_BASE,
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.size = S32V234_IRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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.virt = S32V234_DRAM_BASE1,
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.phys = S32V234_DRAM_BASE1,
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.size = S32V234_DRAM_SIZE1,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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.virt = S32V234_PERIPH_BASE,
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.phys = S32V234_PERIPH_BASE,
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.size = S32V234_PERIPH_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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/* TODO: Do we need these? */
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/* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
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}, {
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.virt = S32V234_DRAM_BASE2,
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.phys = S32V234_DRAM_BASE2,
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.size = S32V234_DRAM_SIZE2,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = s32v234_mem_map;
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#endif
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/*
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* Return the number of cores on this SOC.
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*/
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int cpu_numcores(void)
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{
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int numcores;
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u32 mask;
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mask = cpu_mask();
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numcores = hweight32(cpu_mask());
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/* Verify if M4 is deactivated */
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if (mask & 0x1)
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numcores--;
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return numcores;
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}
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#if defined(CONFIG_ARCH_EARLY_INIT_R)
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int arch_early_init_r(void)
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{
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int rv;
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asm volatile ("dsb sy");
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rv = fsl_s32v234_wake_seconday_cores();
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if (rv)
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printf("Did not wake secondary cores\n");
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asm volatile ("sev");
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return 0;
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}
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#endif /* CONFIG_ARCH_EARLY_INIT_R */
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@@ -1,7 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
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*/
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u32 cpu_mask(void);
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int cpu_numcores(void);
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@@ -1,354 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mc_cgm_regs.h>
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#include <asm/arch/mc_me_regs.h>
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#include <asm/arch/mc_rgm_regs.h>
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#include <netdev.h>
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#include <div64.h>
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#include <errno.h>
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u32 get_cpu_rev(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
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u32 cpu = readl(&mscmir->cpxtype);
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return cpu;
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}
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DECLARE_GLOBAL_DATA_PTR;
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static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
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u32 pllfd, u32 selected_output)
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{
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u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
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u32 plldv_rfdphi_div = 0, fout = 0;
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u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
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if (selected_output > DFS_MAXNUMBER) {
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return -1;
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}
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plldv_prediv =
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(plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
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plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
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pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
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plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
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/* The formula for VCO is from TR manual, rev. D */
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vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
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if (selected_output != 0) {
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/* Determine the RFDPHI for PHI1 */
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plldv_rfdphi_div =
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(plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
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PLLDIG_PLLDV_RFDPHI1_OFFSET;
|
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plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
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if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
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dfs_portn =
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readl(DFS_DVPORTn(pll, selected_output - 1));
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dfs_mfi =
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(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
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DFS_DVPORTn_MFI_OFFSET;
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dfs_mfn =
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(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
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DFS_DVPORTn_MFI_OFFSET;
|
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fout = vco / (dfs_mfi + (dfs_mfn / 256));
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} else {
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fout = vco / plldv_rfdphi_div;
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}
|
||||
|
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} else {
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/* Determine the RFDPHI for PHI0 */
|
||||
plldv_rfdphi_div =
|
||||
(plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
|
||||
PLLDIG_PLLDV_RFDPHI_OFFSET;
|
||||
fout = vco / plldv_rfdphi_div;
|
||||
}
|
||||
|
||||
return fout;
|
||||
|
||||
}
|
||||
|
||||
/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
|
||||
static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
|
||||
u32 selected_output)
|
||||
{
|
||||
u32 plldv, pllfd;
|
||||
|
||||
plldv = readl(PLLDIG_PLLDV(pll));
|
||||
pllfd = readl(PLLDIG_PLLFD(pll));
|
||||
|
||||
return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
|
||||
}
|
||||
|
||||
static u32 get_mcu_main_clk(void)
|
||||
{
|
||||
u32 coreclk_div;
|
||||
u32 sysclk_sel;
|
||||
u32 freq = 0;
|
||||
|
||||
sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
|
||||
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
|
||||
|
||||
coreclk_div =
|
||||
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
|
||||
coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
|
||||
coreclk_div += 1;
|
||||
|
||||
switch (sysclk_sel) {
|
||||
case MC_CGM_SC_SEL_FIRC:
|
||||
freq = FIRC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_SC_SEL_XOSC:
|
||||
freq = XOSC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_SC_SEL_ARMPLL:
|
||||
/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
|
||||
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
|
||||
break;
|
||||
case MC_CGM_SC_SEL_CLKDISABLE:
|
||||
printf("Sysclk is disabled\n");
|
||||
break;
|
||||
default:
|
||||
printf("unsupported system clock select\n");
|
||||
}
|
||||
|
||||
return freq / coreclk_div;
|
||||
}
|
||||
|
||||
static u32 get_sys_clk(u32 number)
|
||||
{
|
||||
u32 sysclk_div, sysclk_div_number;
|
||||
u32 sysclk_sel;
|
||||
u32 freq = 0;
|
||||
|
||||
switch (number) {
|
||||
case 3:
|
||||
sysclk_div_number = 0;
|
||||
break;
|
||||
case 6:
|
||||
sysclk_div_number = 1;
|
||||
break;
|
||||
default:
|
||||
printf("unsupported system clock \n");
|
||||
return -1;
|
||||
}
|
||||
sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
|
||||
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
|
||||
|
||||
sysclk_div =
|
||||
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
|
||||
MC_CGM_SC_DCn_PREDIV_MASK;
|
||||
sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
|
||||
sysclk_div += 1;
|
||||
|
||||
switch (sysclk_sel) {
|
||||
case MC_CGM_SC_SEL_FIRC:
|
||||
freq = FIRC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_SC_SEL_XOSC:
|
||||
freq = XOSC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_SC_SEL_ARMPLL:
|
||||
/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
|
||||
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
|
||||
break;
|
||||
case MC_CGM_SC_SEL_CLKDISABLE:
|
||||
printf("Sysclk is disabled\n");
|
||||
break;
|
||||
default:
|
||||
printf("unsupported system clock select\n");
|
||||
}
|
||||
|
||||
return freq / sysclk_div;
|
||||
}
|
||||
|
||||
static u32 get_peripherals_clk(void)
|
||||
{
|
||||
u32 aux5clk_div;
|
||||
u32 freq = 0;
|
||||
|
||||
aux5clk_div =
|
||||
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
|
||||
MC_CGM_ACn_DCm_PREDIV_MASK;
|
||||
aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
|
||||
aux5clk_div += 1;
|
||||
|
||||
freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
|
||||
|
||||
return freq / aux5clk_div;
|
||||
|
||||
}
|
||||
|
||||
static u32 get_uart_clk(void)
|
||||
{
|
||||
u32 auxclk3_div, auxclk3_sel, freq = 0;
|
||||
|
||||
auxclk3_sel =
|
||||
readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
|
||||
auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
|
||||
|
||||
auxclk3_div =
|
||||
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
|
||||
MC_CGM_ACn_DCm_PREDIV_MASK;
|
||||
auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
|
||||
auxclk3_div += 1;
|
||||
|
||||
switch (auxclk3_sel) {
|
||||
case MC_CGM_ACn_SEL_FIRC:
|
||||
freq = FIRC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_ACn_SEL_XOSC:
|
||||
freq = XOSC_CLK_FREQ;
|
||||
break;
|
||||
case MC_CGM_ACn_SEL_PERPLLDIVX:
|
||||
freq = get_peripherals_clk() / 3;
|
||||
break;
|
||||
case MC_CGM_ACn_SEL_SYSCLK:
|
||||
freq = get_sys_clk(6);
|
||||
break;
|
||||
default:
|
||||
printf("unsupported system clock select\n");
|
||||
}
|
||||
|
||||
return freq / auxclk3_div;
|
||||
}
|
||||
|
||||
static u32 get_fec_clk(void)
|
||||
{
|
||||
u32 aux2clk_div;
|
||||
u32 freq = 0;
|
||||
|
||||
aux2clk_div =
|
||||
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
|
||||
MC_CGM_ACn_DCm_PREDIV_MASK;
|
||||
aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
|
||||
aux2clk_div += 1;
|
||||
|
||||
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
|
||||
|
||||
return freq / aux2clk_div;
|
||||
}
|
||||
|
||||
static u32 get_usdhc_clk(void)
|
||||
{
|
||||
u32 aux15clk_div;
|
||||
u32 freq = 0;
|
||||
|
||||
aux15clk_div =
|
||||
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
|
||||
MC_CGM_ACn_DCm_PREDIV_MASK;
|
||||
aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
|
||||
aux15clk_div += 1;
|
||||
|
||||
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
|
||||
|
||||
return freq / aux15clk_div;
|
||||
}
|
||||
|
||||
static u32 get_i2c_clk(void)
|
||||
{
|
||||
return get_peripherals_clk();
|
||||
}
|
||||
|
||||
/* return clocks in Hz */
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_ARM_CLK:
|
||||
return get_mcu_main_clk();
|
||||
case MXC_PERIPHERALS_CLK:
|
||||
return get_peripherals_clk();
|
||||
case MXC_UART_CLK:
|
||||
return get_uart_clk();
|
||||
case MXC_FEC_CLK:
|
||||
return get_fec_clk();
|
||||
case MXC_I2C_CLK:
|
||||
return get_i2c_clk();
|
||||
case MXC_USDHC_CLK:
|
||||
return get_usdhc_clk();
|
||||
default:
|
||||
break;
|
||||
}
|
||||
printf("Error: Unsupported function to read the frequency! \
|
||||
Please define it correctly!");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Not yet implemented - int soc_clk_dump(); */
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
|
||||
|
||||
switch (cause) {
|
||||
case F_SWT4:
|
||||
return "WDOG";
|
||||
case F_JTAG:
|
||||
return "JTAG";
|
||||
case F_FCCU_SOFT:
|
||||
return "FCCU soft reaction";
|
||||
case F_FCCU_HARD:
|
||||
return "FCCU hard reaction";
|
||||
case F_SOFT_FUNC:
|
||||
return "Software Functional reset";
|
||||
case F_ST_DONE:
|
||||
return "Self Test done reset";
|
||||
case F_EXT_RST:
|
||||
return "External reset";
|
||||
default:
|
||||
return "unknown reset";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#define SRC_SCR_SW_RST (1<<12)
|
||||
|
||||
void reset_cpu(void)
|
||||
{
|
||||
printf("Feature not supported.\n");
|
||||
};
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
printf("Reset cause: %s\n", get_reset_cause());
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_eth_init(struct bd_info * bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
rc = fecmxc_initialize(bis);
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int get_clocks(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
@@ -1071,10 +1071,6 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
|
||||
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
|
||||
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
|
||||
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
|
||||
dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
|
||||
|
||||
@@ -1,437 +0,0 @@
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* Motherboard Express uATX
|
||||
* V2M-P1
|
||||
*
|
||||
* HBI-0190D
|
||||
*
|
||||
* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
|
||||
* Technical Reference Manual)
|
||||
*
|
||||
* WARNING! The hardware described in this file is independent from the
|
||||
* original variant (vexpress-v2m.dtsi), but there is a strong
|
||||
* correspondence between the two configurations.
|
||||
*
|
||||
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
||||
* CHANGES TO vexpress-v2m.dtsi!
|
||||
*/
|
||||
|
||||
/ {
|
||||
smb@8000000 {
|
||||
motherboard {
|
||||
model = "V2M-P1";
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<4 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
psram@1,00000000 {
|
||||
compatible = "arm,vexpress-psram", "mtd-ram";
|
||||
reg = <1 0x00000000 0x02000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
ethernet@2,02000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <2 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&v2m_fixed_3v3>;
|
||||
vddvario-supply = <&v2m_fixed_3v3>;
|
||||
};
|
||||
|
||||
usb@2,03000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <2 0x03000000 0x20000>;
|
||||
interrupts = <16>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
v2m_sysreg: sysreg@10000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x010000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x10000 0x1000>;
|
||||
|
||||
v2m_led_gpios: gpio@8 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
reg = <0x008 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_mmc_gpios: gpio@48 {
|
||||
compatible = "arm,vexpress-sysreg,sys_mci";
|
||||
reg = <0x048 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_flash_gpios: gpio@4c {
|
||||
compatible = "arm,vexpress-sysreg,sys_flash";
|
||||
reg = <0x04c 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_sysctl: sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
/* PCI-E I2C bus */
|
||||
v2m_i2c_pcie: i2c@30000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x030000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie-switch@60 {
|
||||
compatible = "idt,89hpes32h8";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
aaci@40000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x040000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9>, <10>;
|
||||
cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@60000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@70000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@90000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI I2C bus */
|
||||
v2m_i2c_dvi: i2c@160000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x160000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dvi-transmitter@39 {
|
||||
compatible = "sil,sii9022-tpi", "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dvi_bridge_in: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dvi-transmitter@60 {
|
||||
compatible = "sil,sii9022-cpi", "sil,sii9022";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
compact-flash@1a0000 {
|
||||
compatible = "arm,vexpress-cf", "ata-generic";
|
||||
reg = <0x1a0000 0x100
|
||||
0x1a0100 0xf00>;
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
clcd@1f0000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f0000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&smbclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 800x600 16bpp @36MHz works fine */
|
||||
max-memory-bandwidth = <54000000>;
|
||||
memory-region = <&vram>;
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: fixed-regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user1 {
|
||||
label = "v2m:green:user1";
|
||||
gpios = <&v2m_led_gpios 0 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "v2m:green:user2";
|
||||
gpios = <&v2m_led_gpios 1 0>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
user3 {
|
||||
label = "v2m:green:user3";
|
||||
gpios = <&v2m_led_gpios 2 0>;
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
||||
user4 {
|
||||
label = "v2m:green:user4";
|
||||
gpios = <&v2m_led_gpios 3 0>;
|
||||
linux,default-trigger = "cpu1";
|
||||
};
|
||||
|
||||
user5 {
|
||||
label = "v2m:green:user5";
|
||||
gpios = <&v2m_led_gpios 4 0>;
|
||||
linux,default-trigger = "cpu2";
|
||||
};
|
||||
|
||||
user6 {
|
||||
label = "v2m:green:user6";
|
||||
gpios = <&v2m_led_gpios 5 0>;
|
||||
linux,default-trigger = "cpu3";
|
||||
};
|
||||
|
||||
user7 {
|
||||
label = "v2m:green:user7";
|
||||
gpios = <&v2m_led_gpios 6 0>;
|
||||
linux,default-trigger = "cpu4";
|
||||
};
|
||||
|
||||
user8 {
|
||||
label = "v2m:green:user8";
|
||||
gpios = <&v2m_led_gpios 7 0>;
|
||||
linux,default-trigger = "cpu5";
|
||||
};
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
||||
/* MCC static memory clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 65000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: oscclk2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt-vio {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp-mcc {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,451 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* Motherboard Express uATX
|
||||
* V2M-P1
|
||||
*
|
||||
* HBI-0190D
|
||||
*
|
||||
* Original memory map ("Legacy memory map" in the board's
|
||||
* Technical Reference Manual)
|
||||
*
|
||||
* WARNING! The hardware described in this file is independent from the
|
||||
* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
|
||||
* correspondence between the two configurations.
|
||||
*
|
||||
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
||||
* CHANGES TO vexpress-v2m-rs1.dtsi!
|
||||
*/
|
||||
|
||||
/ {
|
||||
smb@4000000 {
|
||||
motherboard {
|
||||
model = "V2M-P1";
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<1 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
psram@2,00000000 {
|
||||
compatible = "arm,vexpress-psram", "mtd-ram";
|
||||
reg = <2 0x00000000 0x02000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
ethernet@3,02000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <3 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&v2m_fixed_3v3>;
|
||||
vddvario-supply = <&v2m_fixed_3v3>;
|
||||
};
|
||||
|
||||
usb@3,03000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <3 0x03000000 0x20000>;
|
||||
interrupts = <16>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
iofpga@7,00000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 7 0 0x20000>;
|
||||
|
||||
v2m_sysreg: sysreg@0 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x00000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x1000>;
|
||||
|
||||
v2m_led_gpios: gpio@8 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
reg = <0x008 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_mmc_gpios: gpio@48 {
|
||||
compatible = "arm,vexpress-sysreg,sys_mci";
|
||||
reg = <0x048 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_flash_gpios: gpio@4c {
|
||||
compatible = "arm,vexpress-sysreg,sys_flash";
|
||||
reg = <0x04c 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_sysctl: sysctl@1000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x01000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
/* PCI-E I2C bus */
|
||||
v2m_i2c_pcie: i2c@2000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x02000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie-switch@60 {
|
||||
compatible = "idt,89hpes32h8";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
aaci@4000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x04000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@5000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x05000 0x1000>;
|
||||
interrupts = <9>, <10>;
|
||||
cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@6000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x06000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@7000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x07000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@9000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x09000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@11000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x11000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@12000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI I2C bus */
|
||||
v2m_i2c_dvi: i2c@16000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x16000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dvi-transmitter@39 {
|
||||
compatible = "sil,sii9022-tpi", "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* Both the core tile and the motherboard routes their output
|
||||
* pads to this transmitter. The motherboard system controller
|
||||
* can select one of them as input using a mux register in
|
||||
* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
|
||||
* the only platform with this specific set-up.
|
||||
*/
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dvi_bridge_in_ct: endpoint {
|
||||
remote-endpoint = <&clcd_pads_ct>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dvi_bridge_in_mb: endpoint {
|
||||
remote-endpoint = <&clcd_pads_mb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dvi-transmitter@60 {
|
||||
compatible = "sil,sii9022-cpi", "sil,sii9022";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@17000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x17000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
compact-flash@1a000 {
|
||||
compatible = "arm,vexpress-cf", "ata-generic";
|
||||
reg = <0x1a000 0x100
|
||||
0x1a100 0xf00>;
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
|
||||
clcd@1f000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&smbclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 800x600 16bpp @36MHz works fine */
|
||||
max-memory-bandwidth = <54000000>;
|
||||
memory-region = <&vram>;
|
||||
|
||||
port {
|
||||
clcd_pads_mb: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in_mb>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: fixed-regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user1 {
|
||||
label = "v2m:green:user1";
|
||||
gpios = <&v2m_led_gpios 0 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "v2m:green:user2";
|
||||
gpios = <&v2m_led_gpios 1 0>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
user3 {
|
||||
label = "v2m:green:user3";
|
||||
gpios = <&v2m_led_gpios 2 0>;
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
||||
user4 {
|
||||
label = "v2m:green:user4";
|
||||
gpios = <&v2m_led_gpios 3 0>;
|
||||
linux,default-trigger = "cpu1";
|
||||
};
|
||||
|
||||
user5 {
|
||||
label = "v2m:green:user5";
|
||||
gpios = <&v2m_led_gpios 4 0>;
|
||||
linux,default-trigger = "cpu2";
|
||||
};
|
||||
|
||||
user6 {
|
||||
label = "v2m:green:user6";
|
||||
gpios = <&v2m_led_gpios 5 0>;
|
||||
linux,default-trigger = "cpu3";
|
||||
};
|
||||
|
||||
user7 {
|
||||
label = "v2m:green:user7";
|
||||
gpios = <&v2m_led_gpios 6 0>;
|
||||
linux,default-trigger = "cpu4";
|
||||
};
|
||||
|
||||
user8 {
|
||||
label = "v2m:green:user8";
|
||||
gpios = <&v2m_led_gpios 7 0>;
|
||||
linux,default-trigger = "cpu5";
|
||||
};
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
||||
/* MCC static memory clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 65000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: oscclk2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt-vio {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp-mcc {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,682 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A15x2 A7x3
|
||||
* Cortex-A15_A7 MPCore (V2P-CA15_A7)
|
||||
*
|
||||
* HBI-0249A
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m-rs1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA15_CA7";
|
||||
arm,hbi = <0x249>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <990>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <990>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
cpu4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CLUSTER_SLEEP_BIG: cluster-sleep-big {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 2 is physically at 0x18000000 */
|
||||
vram: vram@18000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0x18000000 0 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
wdt@2a490000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0 0x2a490000 0 0x1000>;
|
||||
interrupts = <0 98 4>;
|
||||
clocks = <&oscclk6a>, <&oscclk6a>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x2b000000 0 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&hdlcd_clk>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2b0a0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0 0x2b0a0000 0 0x1000>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x2c001000 0 0x1000>,
|
||||
<0 0x2c002000 0 0x2000>,
|
||||
<0 0x2c004000 0 0x2000>,
|
||||
<0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
cci@2c090000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0x2c090000 0 0x1000>;
|
||||
ranges = <0x0 0x0 0x2c090000 0x10000>;
|
||||
|
||||
cci_control1: slave-if@4000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control2: slave-if@5000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
pmu@9000 {
|
||||
compatible = "arm,cci-400-pmu,r0";
|
||||
reg = <0x9000 0x5000>;
|
||||
interrupts = <0 105 4>,
|
||||
<0 101 4>,
|
||||
<0 102 4>,
|
||||
<0 103 4>,
|
||||
<0 104 4>;
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0 0x7ff00000 0 0x1000>;
|
||||
interrupts = <0 92 4>,
|
||||
<0 88 4>,
|
||||
<0 89 4>,
|
||||
<0 90 4>,
|
||||
<0 91 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
scc@7fff0000 {
|
||||
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
|
||||
reg = <0 0x7fff0000 0 0x1000>;
|
||||
interrupts = <0 95 4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
pmu-a15 {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
<0 69 4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>;
|
||||
};
|
||||
|
||||
pmu-a7 {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <0 128 4>,
|
||||
<0 129 4>,
|
||||
<0 130 4>;
|
||||
interrupt-affinity = <&cpu2>,
|
||||
<&cpu3>,
|
||||
<&cpu4>;
|
||||
};
|
||||
|
||||
oscclk6a: oscclk6a {
|
||||
/* Reference 24MHz clock */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "oscclk6a";
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
||||
/* A15 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
oscclk1 {
|
||||
/* A15 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
oscclk2 {
|
||||
/* A7 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
oscclk3 {
|
||||
/* A7 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
oscclk4 {
|
||||
/* External AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
hdlcd_clk: oscclk5 {
|
||||
/* HDLCD PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
smbclk: oscclk6 {
|
||||
/* Static memory controller clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 6>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk6";
|
||||
};
|
||||
|
||||
oscclk7 {
|
||||
/* SYS PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 7>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk7";
|
||||
};
|
||||
|
||||
oscclk8 {
|
||||
/* DDR2 PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 8>;
|
||||
freq-range = <20000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk8";
|
||||
};
|
||||
|
||||
volt-a15 {
|
||||
/* A15 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "A15 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A15 Vcore";
|
||||
};
|
||||
|
||||
volt-a7 {
|
||||
/* A7 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "A7 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A7 Vcore";
|
||||
};
|
||||
|
||||
amp-a15 {
|
||||
/* Total current for the two A15 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "A15 Icore";
|
||||
};
|
||||
|
||||
amp-a7 {
|
||||
/* Total current for the three A7 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "A7 Icore";
|
||||
};
|
||||
|
||||
temp-dcc {
|
||||
/* DCC internal temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
|
||||
power-a15 {
|
||||
/* Total power for the two A15 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "A15 Pcore";
|
||||
};
|
||||
|
||||
power-a7 {
|
||||
/* Total power for the three A7 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "A7 Pcore";
|
||||
};
|
||||
|
||||
energy-a15 {
|
||||
/* Total energy for the two A15 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
||||
label = "A15 Jcore";
|
||||
};
|
||||
|
||||
energy-a7 {
|
||||
/* Total energy for the three A7 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 2>, <13 3>;
|
||||
label = "A7 Jcore";
|
||||
};
|
||||
};
|
||||
|
||||
etb@20010000 {
|
||||
compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
etb_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator {
|
||||
/* non-configurable replicators don't show up on the
|
||||
* AMBA bus. As such no need to add "arm,primecell".
|
||||
*/
|
||||
compatible = "arm,coresight-replicator";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&etb_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
remote-endpoint = <&funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@20040000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x20040000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
funnel_out_port0: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&ptm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&ptm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel_in_port2: endpoint {
|
||||
remote-endpoint = <&etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Input port #3 is for ITM, not supported here */
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
funnel_in_port4: endpoint {
|
||||
remote-endpoint = <&etm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
funnel_in_port5: endpoint {
|
||||
remote-endpoint = <&etm2_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@2201c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201c000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu0>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@2201d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201d000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu1>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203c000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu2>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203d000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu3>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203e000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203e000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x3fef0000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
@@ -1,280 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A5x2
|
||||
* Cortex-A5 MPCore (V2P-CA5s)
|
||||
*
|
||||
* HBI-0225B
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m-rs1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 2 is physically at 0x18000000 */
|
||||
vram: vram@18000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x18000000 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
hdlcd@2a110000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0x2a110000 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&hdlcd_clk>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2a150000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x2a150000 0x1000>;
|
||||
clocks = <&axi_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@2a190000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0x2a190000 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&axi_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
scu@2c000000 {
|
||||
compatible = "arm,cortex-a5-scu";
|
||||
reg = <0x2c000000 0x58>;
|
||||
};
|
||||
|
||||
timer@2c000600 {
|
||||
compatible = "arm,cortex-a5-twd-timer";
|
||||
reg = <0x2c000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
timer@2c000200 {
|
||||
compatible = "arm,cortex-a5-global-timer",
|
||||
"arm,cortex-a9-global-timer";
|
||||
reg = <0x2c000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
clocks = <&cpu_clk>;
|
||||
};
|
||||
|
||||
watchdog@2c000620 {
|
||||
compatible = "arm,cortex-a5-twd-wdt";
|
||||
reg = <0x2c000620 0x20>;
|
||||
interrupts = <1 14 0x304>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@2c0f0000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x2c0f0000 0x1000>;
|
||||
interrupts = <0 84 4>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a5-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
<0 69 4>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
cpu_clk: oscclk0 {
|
||||
/* CPU and internal AXI reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <50000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
axi_clk: oscclk1 {
|
||||
/* Multiplexed AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <5000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
oscclk2 {
|
||||
/* DDR2 */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <80000000 120000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
hdlcd_clk: oscclk3 {
|
||||
/* HDLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
oscclk4 {
|
||||
/* Test chip gate configuration */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <80000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
smbclk: oscclk5 {
|
||||
/* SMB clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
temp-dcc {
|
||||
/* DCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x04000000>,
|
||||
<1 0 0x14000000 0x04000000>,
|
||||
<2 0 0x18000000 0x04000000>,
|
||||
<3 0 0x1c000000 0x04000000>,
|
||||
<4 0 0x0c000000 0x04000000>,
|
||||
<5 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40000000 0x40000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
@@ -1,368 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A9x4
|
||||
* Cortex-A9 MPCore (V2P-CA9)
|
||||
*
|
||||
* HBI-0191B
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA9";
|
||||
arm,hbi = <0x191>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A9_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 3 is physically at 0x4c000000 */
|
||||
vram: vram@4c000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x4c000000 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&oscclk1>, <&oscclk2>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 1024x768 16bpp @65MHz */
|
||||
max-memory-bandwidth = <95000000>;
|
||||
|
||||
port {
|
||||
clcd_pads_ct: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in_ct>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@100e0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x100e0000 0x1000>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@100e1000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0x100e1000 0x1000>;
|
||||
interrupts = <0 45 4>,
|
||||
<0 46 4>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer@100e4000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x100e4000 0x1000>;
|
||||
interrupts = <0 48 4>,
|
||||
<0 49 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "timclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@100e5000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x100e5000 0x1000>;
|
||||
interrupts = <0 51 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
scu@1e000000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1e000000 0x58>;
|
||||
};
|
||||
|
||||
timer@1e000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1e000600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
watchdog@1e000620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x1e000620 0x20>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1e001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1e001000 0x1000>,
|
||||
<0x1e000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@1e00a000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x1e00a000 0x1000>;
|
||||
interrupts = <0 43 4>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
|
||||
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0: extsaxiclk {
|
||||
/* ACLK clock to the AXI master port on the test chip */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <30000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extsaxiclk";
|
||||
};
|
||||
|
||||
oscclk1: clcdclk {
|
||||
/* Reference clock for the CLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <10000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clcdclk";
|
||||
};
|
||||
|
||||
smbclk: oscclk2: tcrefclk {
|
||||
/* Reference clock for the test chip internal PLLs */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <33000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "tcrefclk";
|
||||
};
|
||||
|
||||
volt-vd10 {
|
||||
/* Test Chip internal logic voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VD10";
|
||||
regulator-always-on;
|
||||
label = "VD10";
|
||||
};
|
||||
|
||||
volt-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "VD10_S2";
|
||||
regulator-always-on;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
volt-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 2>;
|
||||
regulator-name = "VD10_S3";
|
||||
regulator-always-on;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
volt-vcc1v8 {
|
||||
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 3>;
|
||||
regulator-name = "VCC1V8";
|
||||
regulator-always-on;
|
||||
label = "VCC1V8";
|
||||
};
|
||||
|
||||
volt-ddr2vtt {
|
||||
/* DDR2 SDRAM VTT termination voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 4>;
|
||||
regulator-name = "DDR2VTT";
|
||||
regulator-always-on;
|
||||
label = "DDR2VTT";
|
||||
};
|
||||
|
||||
volt-vcc3v3 {
|
||||
/* Local board supply for miscellaneous logic external to the Test Chip */
|
||||
arm,vexpress-sysreg,func = <2 5>;
|
||||
compatible = "arm,vexpress-volt";
|
||||
regulator-name = "VCC3V3";
|
||||
regulator-always-on;
|
||||
label = "VCC3V3";
|
||||
};
|
||||
|
||||
amp-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
amp-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
power-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "PVD10_S2";
|
||||
};
|
||||
|
||||
power-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "PVD10_S3";
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@4000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@e0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xe0000000 0x20000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
@@ -1,31 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_BUS_CLK,
|
||||
MXC_PERIPHERALS_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_USDHC_CLK,
|
||||
MXC_FEC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
};
|
||||
enum pll_type {
|
||||
ARM_PLL = 0,
|
||||
PERIPH_PLL,
|
||||
ENET_PLL,
|
||||
DDR_PLL,
|
||||
VIDEO_PLL,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
void clock_init(void);
|
||||
|
||||
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
@@ -1,156 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_DDR_H__
|
||||
|
||||
#define DDR0 0
|
||||
#define DDR1 1
|
||||
|
||||
/* DDR offset in MSCR register */
|
||||
#define _DDR0_RESET 168
|
||||
#define _DDR0_CLK0 169
|
||||
#define _DDR0_CAS 170
|
||||
#define _DDR0_RAS 171
|
||||
#define _DDR0_WE_B 172
|
||||
#define _DDR0_CKE0 173
|
||||
#define _DDR0_CKE1 174
|
||||
#define _DDR0_CS_B0 175
|
||||
#define _DDR0_CS_B1 176
|
||||
#define _DDR0_BA0 177
|
||||
#define _DDR0_BA1 178
|
||||
#define _DDR0_BA2 179
|
||||
#define _DDR0_A0 180
|
||||
#define _DDR0_A1 181
|
||||
#define _DDR0_A2 182
|
||||
#define _DDR0_A3 183
|
||||
#define _DDR0_A4 184
|
||||
#define _DDR0_A5 185
|
||||
#define _DDR0_A6 186
|
||||
#define _DDR0_A7 187
|
||||
#define _DDR0_A8 188
|
||||
#define _DDR0_A9 189
|
||||
#define _DDR0_A10 190
|
||||
#define _DDR0_A11 191
|
||||
#define _DDR0_A12 192
|
||||
#define _DDR0_A13 193
|
||||
#define _DDR0_A14 194
|
||||
#define _DDR0_A15 195
|
||||
#define _DDR0_DM0 196
|
||||
#define _DDR0_DM1 197
|
||||
#define _DDR0_DM2 198
|
||||
#define _DDR0_DM3 199
|
||||
#define _DDR0_DQS0 200
|
||||
#define _DDR0_DQS1 201
|
||||
#define _DDR0_DQS2 202
|
||||
#define _DDR0_DQS3 203
|
||||
#define _DDR0_D0 204
|
||||
#define _DDR0_D1 205
|
||||
#define _DDR0_D2 206
|
||||
#define _DDR0_D3 207
|
||||
#define _DDR0_D4 208
|
||||
#define _DDR0_D5 209
|
||||
#define _DDR0_D6 210
|
||||
#define _DDR0_D7 211
|
||||
#define _DDR0_D8 212
|
||||
#define _DDR0_D9 213
|
||||
#define _DDR0_D10 214
|
||||
#define _DDR0_D11 215
|
||||
#define _DDR0_D12 216
|
||||
#define _DDR0_D13 217
|
||||
#define _DDR0_D14 218
|
||||
#define _DDR0_D15 219
|
||||
#define _DDR0_D16 220
|
||||
#define _DDR0_D17 221
|
||||
#define _DDR0_D18 222
|
||||
#define _DDR0_D19 223
|
||||
#define _DDR0_D20 224
|
||||
#define _DDR0_D21 225
|
||||
#define _DDR0_D22 226
|
||||
#define _DDR0_D23 227
|
||||
#define _DDR0_D24 228
|
||||
#define _DDR0_D25 229
|
||||
#define _DDR0_D26 230
|
||||
#define _DDR0_D27 231
|
||||
#define _DDR0_D28 232
|
||||
#define _DDR0_D29 233
|
||||
#define _DDR0_D30 234
|
||||
#define _DDR0_D31 235
|
||||
#define _DDR0_ODT0 236
|
||||
#define _DDR0_ODT1 237
|
||||
#define _DDR0_ZQ 238
|
||||
#define _DDR1_RESET 239
|
||||
#define _DDR1_CLK0 240
|
||||
#define _DDR1_CAS 241
|
||||
#define _DDR1_RAS 242
|
||||
#define _DDR1_WE_B 243
|
||||
#define _DDR1_CKE0 244
|
||||
#define _DDR1_CKE1 245
|
||||
#define _DDR1_CS_B0 246
|
||||
#define _DDR1_CS_B1 247
|
||||
#define _DDR1_BA0 248
|
||||
#define _DDR1_BA1 249
|
||||
#define _DDR1_BA2 250
|
||||
#define _DDR1_A0 251
|
||||
#define _DDR1_A1 252
|
||||
#define _DDR1_A2 253
|
||||
#define _DDR1_A3 254
|
||||
#define _DDR1_A4 255
|
||||
#define _DDR1_A5 256
|
||||
#define _DDR1_A6 257
|
||||
#define _DDR1_A7 258
|
||||
#define _DDR1_A8 259
|
||||
#define _DDR1_A9 260
|
||||
#define _DDR1_A10 261
|
||||
#define _DDR1_A11 262
|
||||
#define _DDR1_A12 263
|
||||
#define _DDR1_A13 264
|
||||
#define _DDR1_A14 265
|
||||
#define _DDR1_A15 266
|
||||
#define _DDR1_DM0 267
|
||||
#define _DDR1_DM1 268
|
||||
#define _DDR1_DM2 269
|
||||
#define _DDR1_DM3 270
|
||||
#define _DDR1_DQS0 271
|
||||
#define _DDR1_DQS1 272
|
||||
#define _DDR1_DQS2 273
|
||||
#define _DDR1_DQS3 274
|
||||
#define _DDR1_D0 275
|
||||
#define _DDR1_D1 276
|
||||
#define _DDR1_D2 277
|
||||
#define _DDR1_D3 278
|
||||
#define _DDR1_D4 279
|
||||
#define _DDR1_D5 280
|
||||
#define _DDR1_D6 281
|
||||
#define _DDR1_D7 282
|
||||
#define _DDR1_D8 283
|
||||
#define _DDR1_D9 284
|
||||
#define _DDR1_D10 285
|
||||
#define _DDR1_D11 286
|
||||
#define _DDR1_D12 287
|
||||
#define _DDR1_D13 288
|
||||
#define _DDR1_D14 289
|
||||
#define _DDR1_D15 290
|
||||
#define _DDR1_D16 291
|
||||
#define _DDR1_D17 292
|
||||
#define _DDR1_D18 293
|
||||
#define _DDR1_D19 294
|
||||
#define _DDR1_D20 295
|
||||
#define _DDR1_D21 296
|
||||
#define _DDR1_D22 297
|
||||
#define _DDR1_D23 298
|
||||
#define _DDR1_D24 299
|
||||
#define _DDR1_D25 300
|
||||
#define _DDR1_D26 301
|
||||
#define _DDR1_D27 302
|
||||
#define _DDR1_D28 303
|
||||
#define _DDR1_D29 304
|
||||
#define _DDR1_D30 305
|
||||
#define _DDR1_D31 306
|
||||
#define _DDR1_ODT0 307
|
||||
#define _DDR1_ODT1 308
|
||||
#define _DDR1_ZQ 309
|
||||
|
||||
#endif
|
||||
@@ -1,328 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX_REGS_H__
|
||||
#define __ASM_ARCH_IMX_REGS_H__
|
||||
|
||||
#define ARCH_MXC
|
||||
|
||||
#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
|
||||
#define IRAM_SIZE 0x00400000 /* 4MB */
|
||||
|
||||
#define AIPS0_BASE_ADDR (0x40000000UL)
|
||||
#define AIPS1_BASE_ADDR (0x40080000UL)
|
||||
|
||||
/* AIPS 0 */
|
||||
#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
|
||||
#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
|
||||
#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
|
||||
#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
|
||||
#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
|
||||
#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
|
||||
#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
|
||||
#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
|
||||
#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
|
||||
#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
|
||||
#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
|
||||
#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
|
||||
#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
|
||||
#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
|
||||
#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
|
||||
#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
|
||||
#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
|
||||
#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
|
||||
#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
|
||||
#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
|
||||
#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
|
||||
#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
|
||||
#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
|
||||
#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
|
||||
#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
|
||||
#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
|
||||
#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
|
||||
#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
|
||||
#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
|
||||
#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
|
||||
#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
|
||||
#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
|
||||
#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
|
||||
#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
|
||||
#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
|
||||
#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
|
||||
#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
|
||||
#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
|
||||
#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
|
||||
#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
|
||||
#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
|
||||
#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
|
||||
#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
|
||||
#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
|
||||
#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
|
||||
#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
|
||||
|
||||
/* AIPS 1 */
|
||||
#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
|
||||
#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
|
||||
#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
|
||||
#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
|
||||
#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
|
||||
#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
|
||||
#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
|
||||
#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
|
||||
#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
|
||||
#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
|
||||
#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
|
||||
#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
|
||||
#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
|
||||
#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
|
||||
#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
|
||||
#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
|
||||
#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
|
||||
#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
|
||||
#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
|
||||
#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
|
||||
#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
|
||||
#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
|
||||
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
|
||||
#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
|
||||
#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
|
||||
#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
|
||||
#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
|
||||
#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
|
||||
#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
|
||||
#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
|
||||
#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
|
||||
#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
|
||||
#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
|
||||
#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
|
||||
#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
|
||||
#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
|
||||
#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
|
||||
#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
|
||||
#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
|
||||
#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
|
||||
#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
|
||||
#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
|
||||
#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
|
||||
|
||||
/* TODO Remove this after the IOMUX framework is implemented */
|
||||
#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
|
||||
|
||||
/* MUX mode and PAD ctrl are in one register */
|
||||
#define CONFIG_IOMUX_SHARE_CONF_REG
|
||||
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
#define I2C_QUIRK_REG
|
||||
|
||||
/* MSCM interrupt router */
|
||||
#define MSCM_IRSPRC_CPn_EN 3
|
||||
#define MSCM_IRSPRC_NUM 176
|
||||
#define MSCM_CPXTYPE_RYPZ_MASK 0xFF
|
||||
#define MSCM_CPXTYPE_RYPZ_OFFSET 0
|
||||
#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
|
||||
#define MSCM_CPXTYPE_PERS_OFFSET 8
|
||||
#define MSCM_CPXTYPE_PERS_A53 0x413533
|
||||
#define MSCM_CPXTYPE_PERS_CM4 0x434d34
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
/* System Reset Controller (SRC) */
|
||||
struct src {
|
||||
u32 bmr1;
|
||||
u32 bmr2;
|
||||
u32 gpr1_boot;
|
||||
u32 reserved_0x00C[61];
|
||||
u32 gpr1;
|
||||
u32 gpr2;
|
||||
u32 gpr3;
|
||||
u32 gpr4;
|
||||
u32 gpr5;
|
||||
u32 gpr6;
|
||||
u32 gpr7;
|
||||
u32 reserved_0x11C[1];
|
||||
u32 gpr9;
|
||||
u32 gpr10;
|
||||
u32 gpr11;
|
||||
u32 gpr12;
|
||||
u32 gpr13;
|
||||
u32 gpr14;
|
||||
u32 gpr15;
|
||||
u32 gpr16;
|
||||
u32 reserved_0x140[1];
|
||||
u32 gpr17;
|
||||
u32 gpr18;
|
||||
u32 gpr19;
|
||||
u32 gpr20;
|
||||
u32 gpr21;
|
||||
u32 gpr22;
|
||||
u32 gpr23;
|
||||
u32 gpr24;
|
||||
u32 gpr25;
|
||||
u32 gpr26;
|
||||
u32 gpr27;
|
||||
u32 reserved_0x16C[5];
|
||||
u32 pcie_config1;
|
||||
u32 ddr_self_ref_ctrl;
|
||||
u32 pcie_config0;
|
||||
u32 reserved_0x18C[4];
|
||||
u32 soc_misc_config2;
|
||||
};
|
||||
|
||||
/* SRC registers definitions */
|
||||
|
||||
/* SRC_GPR1 */
|
||||
#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
|
||||
(SRC_GPR1_PLL_OFFSET + (pll)) )
|
||||
#define SRC_GPR1_PLL_SOURCE_MASK (0x1)
|
||||
|
||||
#define SRC_GPR1_PLL_OFFSET (27)
|
||||
#define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
|
||||
#define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
|
||||
|
||||
/* Periodic Interrupt Timer (PIT) */
|
||||
struct pit_reg {
|
||||
u32 mcr;
|
||||
u32 recv0[55];
|
||||
u32 ltmr64h;
|
||||
u32 ltmr64l;
|
||||
u32 recv1[6];
|
||||
u32 ldval0;
|
||||
u32 cval0;
|
||||
u32 tctrl0;
|
||||
u32 tflg0;
|
||||
u32 ldval1;
|
||||
u32 cval1;
|
||||
u32 tctrl1;
|
||||
u32 tflg1;
|
||||
u32 ldval2;
|
||||
u32 cval2;
|
||||
u32 tctrl2;
|
||||
u32 tflg2;
|
||||
u32 ldval3;
|
||||
u32 cval3;
|
||||
u32 tctrl3;
|
||||
u32 tflg3;
|
||||
u32 ldval4;
|
||||
u32 cval4;
|
||||
u32 tctrl4;
|
||||
u32 tflg4;
|
||||
u32 ldval5;
|
||||
u32 cval5;
|
||||
u32 tctrl5;
|
||||
u32 tflg5;
|
||||
};
|
||||
|
||||
/* Watchdog Timer (WDOG) */
|
||||
struct wdog_regs {
|
||||
u32 cr;
|
||||
u32 ir;
|
||||
u32 to;
|
||||
u32 wn;
|
||||
u32 sr;
|
||||
u32 co;
|
||||
u32 sk;
|
||||
};
|
||||
|
||||
/* UART */
|
||||
struct linflex_fsl {
|
||||
u32 lincr1;
|
||||
u32 linier;
|
||||
u32 linsr;
|
||||
u32 linesr;
|
||||
u32 uartcr;
|
||||
u32 uartsr;
|
||||
u32 lintcsr;
|
||||
u32 linocr;
|
||||
u32 lintocr;
|
||||
u32 linfbrr;
|
||||
u32 linibrr;
|
||||
u32 lincfr;
|
||||
u32 lincr2;
|
||||
u32 bidr;
|
||||
u32 bdrl;
|
||||
u32 bdrm;
|
||||
u32 ifer;
|
||||
u32 ifmi;
|
||||
u32 ifmr;
|
||||
u32 ifcr0;
|
||||
u32 ifcr1;
|
||||
u32 ifcr2;
|
||||
u32 ifcr3;
|
||||
u32 ifcr4;
|
||||
u32 ifcr5;
|
||||
u32 ifcr6;
|
||||
u32 ifcr7;
|
||||
u32 ifcr8;
|
||||
u32 ifcr9;
|
||||
u32 ifcr10;
|
||||
u32 ifcr11;
|
||||
u32 ifcr12;
|
||||
u32 ifcr13;
|
||||
u32 ifcr14;
|
||||
u32 ifcr15;
|
||||
u32 gcr;
|
||||
u32 uartpto;
|
||||
u32 uartcto;
|
||||
u32 dmatxe;
|
||||
u32 dmarxe;
|
||||
};
|
||||
|
||||
/* MSCM Interrupt Router */
|
||||
struct mscm_ir {
|
||||
u32 cpxtype; /* Processor x Type Register */
|
||||
u32 cpxnum; /* Processor x Number Register */
|
||||
u32 cpxmaster; /* Processor x Master Number Register */
|
||||
u32 cpxcount; /* Processor x Count Register */
|
||||
u32 cpxcfg0; /* Processor x Configuration 0 Register */
|
||||
u32 cpxcfg1; /* Processor x Configuration 1 Register */
|
||||
u32 cpxcfg2; /* Processor x Configuration 2 Register */
|
||||
u32 cpxcfg3; /* Processor x Configuration 3 Register */
|
||||
u32 cp0type; /* Processor 0 Type Register */
|
||||
u32 cp0num; /* Processor 0 Number Register */
|
||||
u32 cp0master; /* Processor 0 Master Number Register */
|
||||
u32 cp0count; /* Processor 0 Count Register */
|
||||
u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
|
||||
u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
|
||||
u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
|
||||
u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
|
||||
u32 cp1type; /* Processor 1 Type Register */
|
||||
u32 cp1num; /* Processor 1 Number Register */
|
||||
u32 cp1master; /* Processor 1 Master Number Register */
|
||||
u32 cp1count; /* Processor 1 Count Register */
|
||||
u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
|
||||
u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
|
||||
u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
|
||||
u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
|
||||
u32 reserved_0x060[232];
|
||||
u32 ocmdr0; /* On-Chip Memory Descriptor Register */
|
||||
u32 reserved_0x404[2];
|
||||
u32 ocmdr3; /* On-Chip Memory Descriptor Register */
|
||||
u32 reserved_0x410[28];
|
||||
u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
|
||||
u32 reserved_0x490[28];
|
||||
u32 cpce0; /* Core Parity Checking Enable Register 0 */
|
||||
u32 reserved_0x504[191];
|
||||
u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
|
||||
u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
|
||||
u32 reserved_0x808[6];
|
||||
u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
|
||||
u32 reserved_0x824[23];
|
||||
u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
|
||||
u32 reserved_0x9e0[136];
|
||||
u32 iahbbe0; /* Gasket Burst Enable Register */
|
||||
u32 reserved_0xc04[63];
|
||||
u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
|
||||
u32 reserved_0xd04[3];
|
||||
u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
|
||||
u32 reserved_0xd20[8];
|
||||
u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
|
||||
u32 reserved_0xd44[3];
|
||||
u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|
||||
@@ -1,74 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
|
||||
|
||||
/* definitions for LPDDR2 PAD values */
|
||||
#define LPDDR2_CLK0_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
|
||||
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \
|
||||
SIUL2_MSCR_DCYCLE_TRIM_NONE)
|
||||
#define LPDDR2_CKEn_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
|
||||
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
|
||||
#define LPDDR2_CS_Bn_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
|
||||
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
|
||||
#define LPDDR2_DMn_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
|
||||
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
|
||||
#define LPDDR2_DQSn_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
|
||||
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \
|
||||
SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
|
||||
#define LPDDR2_An_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
|
||||
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
|
||||
SIUL2_MSCR_PUS_100K_UP)
|
||||
#define LPDDR2_Dn_PAD \
|
||||
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
|
||||
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
|
||||
SIUL2_MSCR_PUS_100K_UP)
|
||||
|
||||
#define _MDCTL 0x03010000
|
||||
|
||||
#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */
|
||||
#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
|
||||
#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
|
||||
#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
|
||||
#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
|
||||
#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
|
||||
#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
|
||||
#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
|
||||
#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */
|
||||
#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */
|
||||
#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
|
||||
#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
|
||||
#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
|
||||
#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */
|
||||
#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */
|
||||
#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */
|
||||
#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */
|
||||
#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */
|
||||
#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */
|
||||
#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
|
||||
#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
|
||||
#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */
|
||||
#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */
|
||||
#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */
|
||||
#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
|
||||
#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
|
||||
#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */
|
||||
#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */
|
||||
#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */
|
||||
#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */
|
||||
#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */
|
||||
|
||||
/* set I/O pads for DDR */
|
||||
void lpddr2_config_iomux(uint8_t module);
|
||||
void config_mmdc(uint8_t module);
|
||||
|
||||
#endif
|
||||
@@ -1,253 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* MC_CGM registers definitions */
|
||||
/* MC_CGM_SC_SS */
|
||||
#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) )
|
||||
#define MC_CGM_SC_SEL_FIRC (0x0)
|
||||
#define MC_CGM_SC_SEL_XOSC (0x1)
|
||||
#define MC_CGM_SC_SEL_ARMPLL (0x2)
|
||||
#define MC_CGM_SC_SEL_CLKDISABLE (0xF)
|
||||
|
||||
/* MC_CGM_SC_DCn */
|
||||
#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
|
||||
#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
|
||||
#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000)
|
||||
#define MC_CGM_SC_DCn_PREDIV_OFFSET (16)
|
||||
#define MC_CGM_SC_DCn_DE (1 << 31)
|
||||
#define MC_CGM_SC_SEL_MASK (0x0F000000)
|
||||
#define MC_CGM_SC_SEL_OFFSET (24)
|
||||
|
||||
/* MC_CGM_ACn_DCm */
|
||||
#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
|
||||
#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
|
||||
|
||||
/*
|
||||
* MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
|
||||
* that the 5th bit is always ignored during writes if the current
|
||||
* MC_CGM_ACn_DCm_PREDIV field has only 4 bits
|
||||
*
|
||||
* The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
|
||||
*
|
||||
* This should be changed if any problems occur.
|
||||
*/
|
||||
#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
|
||||
#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16)
|
||||
#define MC_CGM_ACn_DCm_DE (1 << 31)
|
||||
|
||||
/*
|
||||
* MC_CGM_ACn_SC/MC_CGM_ACn_SS
|
||||
*/
|
||||
#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20))
|
||||
#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20))
|
||||
#define MC_CGM_ACn_SEL_MASK (0x07000000)
|
||||
#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
|
||||
#define MC_CGM_ACn_SEL_OFFSET (24)
|
||||
|
||||
#define MC_CGM_ACn_SEL_FIRC (0x0)
|
||||
#define MC_CGM_ACn_SEL_XOSC (0x1)
|
||||
#define MC_CGM_ACn_SEL_ARMPLL (0x2)
|
||||
/*
|
||||
* According to the manual some PLL can be divided by X (X={1,3,5}):
|
||||
* PERPLLDIVX, VIDEOPLLDIVX.
|
||||
*/
|
||||
#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3)
|
||||
#define MC_CGM_ACn_SEL_ENETPLL (0x4)
|
||||
#define MC_CGM_ACn_SEL_DDRPLL (0x5)
|
||||
#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7)
|
||||
#define MC_CGM_ACn_SEL_SYSCLK (0x8)
|
||||
#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9)
|
||||
#define MC_CGM_ACn_SEL_PERCLK (0xA)
|
||||
|
||||
/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
|
||||
#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
|
||||
#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div))
|
||||
#define PLLDIG_PLLDV_MFD_MASK (0x000000FF)
|
||||
|
||||
/*
|
||||
* PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
|
||||
* the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
|
||||
*/
|
||||
#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
|
||||
#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000)
|
||||
#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F)
|
||||
#define PLLDIG_PLLDV_RFDPHI_OFFSET (16)
|
||||
|
||||
#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
|
||||
#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000)
|
||||
#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F)
|
||||
#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25)
|
||||
|
||||
#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
|
||||
#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000)
|
||||
#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7)
|
||||
#define PLLDIG_PLLDV_PREDIV_OFFSET (12)
|
||||
|
||||
/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */
|
||||
#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
|
||||
#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val))
|
||||
#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF)
|
||||
#define PLLDIG_PLLFD_SMDEN (1 << 30)
|
||||
|
||||
/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
|
||||
#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
|
||||
#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
|
||||
#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24)
|
||||
#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000)
|
||||
|
||||
/* Digital Frequency Synthesizer (DFS) */
|
||||
/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
|
||||
#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040)
|
||||
|
||||
/* DFS DLL Program Register 1 */
|
||||
#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
|
||||
|
||||
#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
|
||||
#define DFS_DLLPRG1_V2IGC_OFFSET (0)
|
||||
#define DFS_DLLPRG1_V2IGC_MASK (0x00000007)
|
||||
|
||||
#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
|
||||
#define DFS_DLLPRG1_LCKWT_OFFSET (4)
|
||||
#define DFS_DLLPRG1_LCKWT_MASK (0x00000030)
|
||||
|
||||
#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
|
||||
#define DFS_DLLPRG1_DACIN_OFFSET (6)
|
||||
#define DFS_DLLPRG1_DACIN_MASK (0x000001C0)
|
||||
|
||||
#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
|
||||
#define DFS_DLLPRG1_CALBYPEN_OFFSET (9)
|
||||
#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200)
|
||||
|
||||
#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
|
||||
#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10)
|
||||
#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00)
|
||||
|
||||
#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
|
||||
#define DFS_DLLPRG1_CPICTRL_OFFSET (12)
|
||||
#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000)
|
||||
|
||||
/* DFS Control Register (DFS_CTRL) */
|
||||
#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
|
||||
#define DFS_CTRL_DLL_LOLIE (1 << 0)
|
||||
#define DFS_CTRL_DLL_RESET (1 << 1)
|
||||
|
||||
/* DFS Port Status Register (DFS_PORTSR) */
|
||||
#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
|
||||
/* DFS Port Reset Register (DFS_PORTRESET) */
|
||||
#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
|
||||
#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
|
||||
#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF)
|
||||
#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F)
|
||||
#define DFS_PORTRESET_PORTRESET_OFFSET (0)
|
||||
|
||||
/* DFS Divide Register Portn (DFS_DVPORTn) */
|
||||
#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
|
||||
|
||||
/*
|
||||
* The mathematical formula for fdfs_clockout is the following:
|
||||
* fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
|
||||
*/
|
||||
#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
|
||||
#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
|
||||
#define DFS_DVPORTn_MFI_MASK (0x0000FF00)
|
||||
#define DFS_DVPORTn_MFN_MASK (0x000000FF)
|
||||
#define DFS_DVPORTn_MFI_MAXVAL (0xFF)
|
||||
#define DFS_DVPORTn_MFN_MAXVAL (0xFF)
|
||||
#define DFS_DVPORTn_MFI_OFFSET (8)
|
||||
#define DFS_DVPORTn_MFN_OFFSET (0)
|
||||
#define DFS_MAXNUMBER (4)
|
||||
|
||||
#define DFS_PARAMS_Nr (3)
|
||||
|
||||
/* Frequencies are in Hz */
|
||||
#define FIRC_CLK_FREQ (48000000)
|
||||
#define XOSC_CLK_FREQ (40000000)
|
||||
|
||||
#define PLL_MIN_FREQ (650000000)
|
||||
#define PLL_MAX_FREQ (1300000000)
|
||||
|
||||
#define ARM_PLL_PHI0_FREQ (1000000000)
|
||||
#define ARM_PLL_PHI1_FREQ (1000000000)
|
||||
/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
|
||||
#define ARM_PLL_PHI1_DFS1_EN (1)
|
||||
#define ARM_PLL_PHI1_DFS1_MFI (3)
|
||||
#define ARM_PLL_PHI1_DFS1_MFN (194)
|
||||
/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
|
||||
#define ARM_PLL_PHI1_DFS2_EN (1)
|
||||
#define ARM_PLL_PHI1_DFS2_MFI (1)
|
||||
#define ARM_PLL_PHI1_DFS2_MFN (170)
|
||||
/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
|
||||
#define ARM_PLL_PHI1_DFS3_EN (1)
|
||||
#define ARM_PLL_PHI1_DFS3_MFI (1)
|
||||
#define ARM_PLL_PHI1_DFS3_MFN (170)
|
||||
#define ARM_PLL_PHI1_DFS_Nr (3)
|
||||
#define ARM_PLL_PLLDV_PREDIV (2)
|
||||
#define ARM_PLL_PLLDV_MFD (50)
|
||||
#define ARM_PLL_PLLDV_MFN (0)
|
||||
|
||||
#define PERIPH_PLL_PHI0_FREQ (400000000)
|
||||
#define PERIPH_PLL_PHI1_FREQ (100000000)
|
||||
#define PERIPH_PLL_PHI1_DFS_Nr (0)
|
||||
#define PERIPH_PLL_PLLDV_PREDIV (1)
|
||||
#define PERIPH_PLL_PLLDV_MFD (30)
|
||||
#define PERIPH_PLL_PLLDV_MFN (0)
|
||||
|
||||
#define ENET_PLL_PHI0_FREQ (500000000)
|
||||
#define ENET_PLL_PHI1_FREQ (1000000000)
|
||||
/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
|
||||
#define ENET_PLL_PHI1_DFS1_EN (1)
|
||||
#define ENET_PLL_PHI1_DFS1_MFI (2)
|
||||
#define ENET_PLL_PHI1_DFS1_MFN (219)
|
||||
/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
|
||||
#define ENET_PLL_PHI1_DFS2_EN (1)
|
||||
#define ENET_PLL_PHI1_DFS2_MFI (2)
|
||||
#define ENET_PLL_PHI1_DFS2_MFN (219)
|
||||
/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
|
||||
#define ENET_PLL_PHI1_DFS3_EN (1)
|
||||
#define ENET_PLL_PHI1_DFS3_MFI (3)
|
||||
#define ENET_PLL_PHI1_DFS3_MFN (32)
|
||||
/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
|
||||
#define ENET_PLL_PHI1_DFS4_EN (1)
|
||||
#define ENET_PLL_PHI1_DFS4_MFI (2)
|
||||
#define ENET_PLL_PHI1_DFS4_MFN (0)
|
||||
#define ENET_PLL_PHI1_DFS_Nr (4)
|
||||
#define ENET_PLL_PLLDV_PREDIV (2)
|
||||
#define ENET_PLL_PLLDV_MFD (50)
|
||||
#define ENET_PLL_PLLDV_MFN (0)
|
||||
|
||||
#define DDR_PLL_PHI0_FREQ (533000000)
|
||||
#define DDR_PLL_PHI1_FREQ (1066000000)
|
||||
/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
|
||||
#define DDR_PLL_PHI1_DFS1_EN (1)
|
||||
#define DDR_PLL_PHI1_DFS1_MFI (2)
|
||||
#define DDR_PLL_PHI1_DFS1_MFN (33)
|
||||
/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
|
||||
#define DDR_PLL_PHI1_DFS2_EN (1)
|
||||
#define DDR_PLL_PHI1_DFS2_MFI (2)
|
||||
#define DDR_PLL_PHI1_DFS2_MFN (33)
|
||||
/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
|
||||
#define DDR_PLL_PHI1_DFS3_EN (1)
|
||||
#define DDR_PLL_PHI1_DFS3_MFI (3)
|
||||
#define DDR_PLL_PHI1_DFS3_MFN (11)
|
||||
#define DDR_PLL_PHI1_DFS_Nr (3)
|
||||
#define DDR_PLL_PLLDV_PREDIV (2)
|
||||
#define DDR_PLL_PLLDV_MFD (53)
|
||||
#define DDR_PLL_PLLDV_MFN (6144)
|
||||
|
||||
#define VIDEO_PLL_PHI0_FREQ (600000000)
|
||||
#define VIDEO_PLL_PHI1_FREQ (0)
|
||||
#define VIDEO_PLL_PHI1_DFS_Nr (0)
|
||||
#define VIDEO_PLL_PLLDV_PREDIV (1)
|
||||
#define VIDEO_PLL_PLLDV_MFD (30)
|
||||
#define VIDEO_PLL_PLLDV_MFN (0)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
|
||||
@@ -1,198 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* MC_ME registers definitions */
|
||||
|
||||
/* MC_ME_GS */
|
||||
#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000)
|
||||
|
||||
#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0)
|
||||
#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0)
|
||||
#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0)
|
||||
#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0)
|
||||
#define MC_ME_GS_S_FIRC (1 << 4)
|
||||
#define MC_ME_GS_S_XOSC (1 << 5)
|
||||
#define MC_ME_GS_S_ARMPLL (1 << 6)
|
||||
#define MC_ME_GS_S_PERPLL (1 << 7)
|
||||
#define MC_ME_GS_S_ENETPLL (1 << 8)
|
||||
#define MC_ME_GS_S_DDRPLL (1 << 9)
|
||||
#define MC_ME_GS_S_VIDEOPLL (1 << 10)
|
||||
#define MC_ME_GS_S_MVR (1 << 20)
|
||||
#define MC_ME_GS_S_PDO (1 << 23)
|
||||
#define MC_ME_GS_S_MTRANS (1 << 27)
|
||||
#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28)
|
||||
#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28)
|
||||
|
||||
/* MC_ME_MCTL */
|
||||
#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004)
|
||||
|
||||
#define MC_ME_MCTL_KEY (0x00005AF0)
|
||||
#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F)
|
||||
#define MC_ME_MCTL_RESET (0x0 << 28)
|
||||
#define MC_ME_MCTL_TEST (0x1 << 28)
|
||||
#define MC_ME_MCTL_DRUN (0x3 << 28)
|
||||
#define MC_ME_MCTL_RUN0 (0x4 << 28)
|
||||
#define MC_ME_MCTL_RUN1 (0x5 << 28)
|
||||
#define MC_ME_MCTL_RUN2 (0x6 << 28)
|
||||
#define MC_ME_MCTL_RUN3 (0x7 << 28)
|
||||
|
||||
/* MC_ME_ME */
|
||||
#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008)
|
||||
|
||||
#define MC_ME_ME_RESET_FUNC (1 << 0)
|
||||
#define MC_ME_ME_TEST (1 << 1)
|
||||
#define MC_ME_ME_DRUN (1 << 3)
|
||||
#define MC_ME_ME_RUN0 (1 << 4)
|
||||
#define MC_ME_ME_RUN1 (1 << 5)
|
||||
#define MC_ME_ME_RUN2 (1 << 6)
|
||||
#define MC_ME_ME_RUN3 (1 << 7)
|
||||
|
||||
/* MC_ME_RUN_PCn */
|
||||
#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
|
||||
|
||||
#define MC_ME_RUN_PCn_RESET (1 << 0)
|
||||
#define MC_ME_RUN_PCn_TEST (1 << 1)
|
||||
#define MC_ME_RUN_PCn_DRUN (1 << 3)
|
||||
#define MC_ME_RUN_PCn_RUN0 (1 << 4)
|
||||
#define MC_ME_RUN_PCn_RUN1 (1 << 5)
|
||||
#define MC_ME_RUN_PCn_RUN2 (1 << 6)
|
||||
#define MC_ME_RUN_PCn_RUN3 (1 << 7)
|
||||
|
||||
/*
|
||||
* MC_ME_RESET_MC/MC_ME_TEST_MC
|
||||
* MC_ME_DRUN_MC
|
||||
* MC_ME_RUNn_MC
|
||||
*/
|
||||
#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020)
|
||||
#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024)
|
||||
#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C)
|
||||
#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
|
||||
|
||||
#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
|
||||
#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F)
|
||||
#define MC_ME_RUNMODE_MC_FIRCON (1 << 4)
|
||||
#define MC_ME_RUNMODE_MC_XOSCON (1 << 5)
|
||||
#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll)))
|
||||
#define MC_ME_RUNMODE_MC_MVRON (1 << 20)
|
||||
#define MC_ME_RUNMODE_MC_PDO (1 << 23)
|
||||
#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28)
|
||||
#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29)
|
||||
#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30)
|
||||
|
||||
/* MC_ME_DRUN_SEC_CC_I */
|
||||
#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260)
|
||||
/* MC_ME_RUNn_SEC_CC_I */
|
||||
#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
|
||||
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
|
||||
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4)
|
||||
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8)
|
||||
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12)
|
||||
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3)
|
||||
|
||||
/*
|
||||
* ME_PCTLn
|
||||
* Please note that these registers are 8 bits width, so
|
||||
* the operations over them should be done using 8 bits operations.
|
||||
*/
|
||||
#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
|
||||
#define MC_ME_PCTLn_RUNPCm_MASK (0x7)
|
||||
|
||||
/* DEC200 Peripheral Control Register */
|
||||
#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4)
|
||||
/* 2D-ACE Peripheral Control Register */
|
||||
#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB)
|
||||
/* ENET Peripheral Control Register */
|
||||
#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1)
|
||||
/* DMACHMUX0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2)
|
||||
/* CSI0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3)
|
||||
/* MMDC0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5)
|
||||
/* FRAY Peripheral Control Register */
|
||||
#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7)
|
||||
/* PIT0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9)
|
||||
/* FlexTIMER0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C)
|
||||
/* SARADC0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E)
|
||||
/* LINFLEX0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110)
|
||||
/* IIC0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112)
|
||||
/* DSPI0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114)
|
||||
/* CANFD0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116)
|
||||
/* CRC0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118)
|
||||
/* DSPI2 Peripheral Control Register */
|
||||
#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A)
|
||||
/* SDHC Peripheral Control Register */
|
||||
#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E)
|
||||
/* VIU0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127)
|
||||
/* HPSMI Peripheral Control Register */
|
||||
#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B)
|
||||
/* SIPI Peripheral Control Register */
|
||||
#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137)
|
||||
/* LFAST Peripheral Control Register */
|
||||
#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B)
|
||||
/* MMDC1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161)
|
||||
/* DMACHMUX1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162)
|
||||
/* CSI1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163)
|
||||
/* QUADSPI0 Peripheral Control Register */
|
||||
#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165)
|
||||
/* PIT1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169)
|
||||
/* FlexTIMER1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175)
|
||||
/* IIC2 Peripheral Control Register */
|
||||
#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179)
|
||||
/* IIC1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B)
|
||||
/* CANFD1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D)
|
||||
/* LINFLEX1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F)
|
||||
/* DSPI3 Peripheral Control Register */
|
||||
#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181)
|
||||
/* DSPI1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183)
|
||||
/* TSENS Peripheral Control Register */
|
||||
#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D)
|
||||
/* CRC1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F)
|
||||
/* VIU1 Peripheral Control Register */
|
||||
#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193)
|
||||
/* JPEG Peripheral Control Register */
|
||||
#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197)
|
||||
/* H264_DEC Peripheral Control Register */
|
||||
#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B)
|
||||
/* H264_ENC Peripheral Control Register */
|
||||
#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F)
|
||||
/* MBIST Peripheral Control Register */
|
||||
#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9)
|
||||
|
||||
/* Core status register */
|
||||
#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
|
||||
@@ -1,30 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
|
||||
|
||||
#define MC_RGM_DES (MC_RGM_BASE_ADDR)
|
||||
#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
|
||||
#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
|
||||
#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
|
||||
#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
|
||||
#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
|
||||
#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
|
||||
#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
|
||||
#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
|
||||
#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
|
||||
#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
|
||||
|
||||
/* function reset sources mask */
|
||||
#define F_SWT4 0x8000
|
||||
#define F_JTAG 0x400
|
||||
#define F_FCCU_SOFT 0x40
|
||||
#define F_FCCU_HARD 0x20
|
||||
#define F_SOFT_FUNC 0x8
|
||||
#define F_ST_DONE 0x4
|
||||
#define F_EXT_RST 0x1
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
|
||||
@@ -1,88 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_MMDC_H__
|
||||
|
||||
#define MMDC0 0
|
||||
#define MMDC1 1
|
||||
|
||||
#define MMDC_MDCTL 0x0
|
||||
#define MMDC_MDPDC 0x4
|
||||
#define MMDC_MDOTC 0x8
|
||||
#define MMDC_MDCFG0 0xC
|
||||
#define MMDC_MDCFG1 0x10
|
||||
#define MMDC_MDCFG2 0x14
|
||||
#define MMDC_MDMISC 0x18
|
||||
#define MMDC_MDSCR 0x1C
|
||||
#define MMDC_MDREF 0x20
|
||||
#define MMDC_MDRWD 0x2C
|
||||
#define MMDC_MDOR 0x30
|
||||
#define MMDC_MDMRR 0x34
|
||||
#define MMDC_MDCFG3LP 0x38
|
||||
#define MMDC_MDMR4 0x3C
|
||||
#define MMDC_MDASP 0x40
|
||||
#define MMDC_MAARCR 0x400
|
||||
#define MMDC_MAPSR 0x404
|
||||
#define MMDC_MAEXIDR0 0x408
|
||||
#define MMDC_MAEXIDR1 0x40C
|
||||
#define MMDC_MADPCR0 0x410
|
||||
#define MMDC_MADPCR1 0x414
|
||||
#define MMDC_MADPSR0 0x418
|
||||
#define MMDC_MADPSR1 0x41C
|
||||
#define MMDC_MADPSR2 0x420
|
||||
#define MMDC_MADPSR3 0x424
|
||||
#define MMDC_MADPSR4 0x428
|
||||
#define MMDC_MADPSR5 0x42C
|
||||
#define MMDC_MASBS0 0x430
|
||||
#define MMDC_MASBS1 0x434
|
||||
#define MMDC_MAGENP 0x440
|
||||
#define MMDC_MPZQHWCTRL 0x800
|
||||
#define MMDC_MPWLGCR 0x808
|
||||
#define MMDC_MPWLDECTRL0 0x80C
|
||||
#define MMDC_MPWLDECTRL1 0x810
|
||||
#define MMDC_MPWLDLST 0x814
|
||||
#define MMDC_MPODTCTRL 0x818
|
||||
#define MMDC_MPRDDQBY0DL 0x81C
|
||||
#define MMDC_MPRDDQBY1DL 0x820
|
||||
#define MMDC_MPRDDQBY2DL 0x824
|
||||
#define MMDC_MPRDDQBY3DL 0x828
|
||||
#define MMDC_MPDGCTRL0 0x83C
|
||||
#define MMDC_MPDGCTRL1 0x840
|
||||
#define MMDC_MPDGDLST0 0x844
|
||||
#define MMDC_MPRDDLCTL 0x848
|
||||
#define MMDC_MPRDDLST 0x84C
|
||||
#define MMDC_MPWRDLCTL 0x850
|
||||
#define MMDC_MPWRDLST 0x854
|
||||
#define MMDC_MPZQLP2CTL 0x85C
|
||||
#define MMDC_MPRDDLHWCTL 0x860
|
||||
#define MMDC_MPWRDLHWCTL 0x864
|
||||
#define MMDC_MPRDDLHWST0 0x868
|
||||
#define MMDC_MPRDDLHWST1 0x86C
|
||||
#define MMDC_MPWRDLHWST1 0x870
|
||||
#define MMDC_MPWRDLHWST2 0x874
|
||||
#define MMDC_MPWLHWERR 0x878
|
||||
#define MMDC_MPDGHWST0 0x87C
|
||||
#define MMDC_MPDGHWST1 0x880
|
||||
#define MMDC_MPDGHWST2 0x884
|
||||
#define MMDC_MPDGHWST3 0x888
|
||||
#define MMDC_MPPDCMPR1 0x88C
|
||||
#define MMDC_MPPDCMPR2 0x890
|
||||
#define MMDC_MPSWDAR0 0x894
|
||||
#define MMDC_MPSWDRDR0 0x898
|
||||
#define MMDC_MPSWDRDR1 0x89C
|
||||
#define MMDC_MPSWDRDR2 0x8A0
|
||||
#define MMDC_MPSWDRDR3 0x8A4
|
||||
#define MMDC_MPSWDRDR4 0x8A8
|
||||
#define MMDC_MPSWDRDR5 0x8AC
|
||||
#define MMDC_MPSWDRDR6 0x8B0
|
||||
#define MMDC_MPSWDRDR7 0x8B4
|
||||
#define MMDC_MPMUR0 0x8B8
|
||||
#define MMDC_MPDCCR 0x8C0
|
||||
|
||||
#define MMDC_MPMUR0_FRC_MSR (1 << 11)
|
||||
#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)
|
||||
|
||||
#endif
|
||||
@@ -1,149 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
|
||||
#define __ARCH_ARM_MACH_S32V234_SIUL_H__
|
||||
|
||||
#include "ddr.h"
|
||||
|
||||
#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
|
||||
#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
|
||||
#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
|
||||
#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
|
||||
#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
|
||||
#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
|
||||
#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
|
||||
#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
|
||||
|
||||
#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
|
||||
#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i))
|
||||
|
||||
#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
|
||||
|
||||
/* SIUL2_MSCR specifications as stated in Reference Manual:
|
||||
* 0 - 359 Output Multiplexed Signal Configuration Registers
|
||||
* 512- 1023 Input Multiplexed Signal Configuration Registers */
|
||||
#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240)
|
||||
#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i))
|
||||
|
||||
#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40)
|
||||
#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i))
|
||||
|
||||
#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300)
|
||||
#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i))
|
||||
|
||||
#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500)
|
||||
#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i))
|
||||
|
||||
#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700)
|
||||
#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i))
|
||||
|
||||
#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740)
|
||||
#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i))
|
||||
|
||||
#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780)
|
||||
#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i))
|
||||
|
||||
/* SIUL2_MSCR masks */
|
||||
#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000)
|
||||
#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
|
||||
#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
|
||||
#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
|
||||
#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
|
||||
|
||||
#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000)
|
||||
#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
|
||||
#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
|
||||
|
||||
#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000)
|
||||
#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27)
|
||||
#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27)
|
||||
|
||||
#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000)
|
||||
#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24)
|
||||
#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24)
|
||||
|
||||
#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000)
|
||||
#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22)
|
||||
#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22)
|
||||
#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22)
|
||||
|
||||
#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000)
|
||||
#define SIUL2_MSCR_OBE_EN (1 << 21)
|
||||
|
||||
#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000)
|
||||
#define SIUL2_MSCR_ODE_EN (1 << 20)
|
||||
|
||||
#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000)
|
||||
#define SIUL2_MSCR_IBE_EN (1 << 19)
|
||||
|
||||
#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000)
|
||||
#define SIUL2_MSCR_HYS_EN (1 << 18)
|
||||
|
||||
#define SIUL2_MSCR_INV(v) ((v) & 0x00020000)
|
||||
#define SIUL2_MSCR_INV_EN (1 << 17)
|
||||
|
||||
#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000)
|
||||
#define SIUL2_MSCR_PKE_EN (1 << 16)
|
||||
|
||||
#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000)
|
||||
#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14)
|
||||
#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14)
|
||||
#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14)
|
||||
#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14)
|
||||
|
||||
#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000)
|
||||
#define SIUL2_MSCR_PUE_EN (1 << 13)
|
||||
|
||||
#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800)
|
||||
#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11)
|
||||
#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11)
|
||||
#define SIUL2_MSCR_PUS_100K_UP (2 << 11)
|
||||
#define SIUL2_MSCR_PUS_33K_UP (3 << 11)
|
||||
|
||||
#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700)
|
||||
#define SIUL2_MSCR_DSE_240ohm (1 << 8)
|
||||
#define SIUL2_MSCR_DSE_120ohm (2 << 8)
|
||||
#define SIUL2_MSCR_DSE_80ohm (3 << 8)
|
||||
#define SIUL2_MSCR_DSE_60ohm (4 << 8)
|
||||
#define SIUL2_MSCR_DSE_48ohm (5 << 8)
|
||||
#define SIUL2_MSCR_DSE_40ohm (6 << 8)
|
||||
#define SIUL2_MSCR_DSE_34ohm (7 << 8)
|
||||
|
||||
#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0)
|
||||
#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6)
|
||||
|
||||
#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020)
|
||||
#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f)
|
||||
#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1)
|
||||
#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2)
|
||||
#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3)
|
||||
|
||||
/* UART settings */
|
||||
#define SIUL2_UART0_TXD_PAD 12
|
||||
#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \
|
||||
SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
|
||||
|
||||
#define SIUL2_UART0_MSCR_RXD_PAD 11
|
||||
#define SIUL2_UART0_IMCR_RXD_PAD 200
|
||||
|
||||
#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
|
||||
#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2)
|
||||
|
||||
/* uSDHC settings */
|
||||
#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \
|
||||
SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \
|
||||
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
|
||||
#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
|
||||
#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
|
||||
#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
|
||||
#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
|
||||
|
||||
#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
|
||||
@@ -134,11 +134,6 @@ config TARGET_PM9G45
|
||||
bool "Ronetix pm9g45 board"
|
||||
select AT91SAM9G45
|
||||
|
||||
config TARGET_PICOSAM9G45
|
||||
bool "Mini-box picosam9g45 board"
|
||||
select AT91SAM9M10G45
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_AT91SAM9N12EK
|
||||
bool "Atmel AT91SAM9N12-EK board"
|
||||
select AT91SAM9N12
|
||||
@@ -303,19 +298,6 @@ config TARGET_VINCO
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_WB45N
|
||||
bool "Support Laird WB45N"
|
||||
select CPU_ARM926EJS
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_WB50N
|
||||
bool "Support Laird WB50N"
|
||||
select BOARD_EARLY_INIT_F
|
||||
select BOARD_LATE_INIT
|
||||
select CPU_V7A
|
||||
select SUPPORT_SPL
|
||||
select ATMEL_SFR
|
||||
|
||||
endchoice
|
||||
|
||||
config ATMEL_SFR
|
||||
@@ -351,15 +333,12 @@ source "board/egnite/ethernut5/Kconfig"
|
||||
source "board/esd/meesc/Kconfig"
|
||||
source "board/gardena/smart-gateway-at91sam/Kconfig"
|
||||
source "board/l+g/vinco/Kconfig"
|
||||
source "board/mini-box/picosam9g45/Kconfig"
|
||||
source "board/ronetix/pm9261/Kconfig"
|
||||
source "board/ronetix/pm9263/Kconfig"
|
||||
source "board/ronetix/pm9g45/Kconfig"
|
||||
source "board/siemens/corvus/Kconfig"
|
||||
source "board/siemens/taurus/Kconfig"
|
||||
source "board/siemens/smartweb/Kconfig"
|
||||
source "board/laird/wb45n/Kconfig"
|
||||
source "board/laird/wb50n/Kconfig"
|
||||
|
||||
config SPL_LDSCRIPT
|
||||
default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
|
||||
|
||||
@@ -52,11 +52,6 @@ config TARGET_MX53CX9020
|
||||
select MX53
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_MX53EVK
|
||||
bool "Support mx53evk"
|
||||
select BOARD_LATE_INIT
|
||||
select MX53
|
||||
|
||||
config TARGET_MX53LOCO
|
||||
bool "Support mx53loco"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -68,10 +63,6 @@ config TARGET_MX53PPD
|
||||
help
|
||||
Enable support for the GE Healthcare PPD.
|
||||
|
||||
config TARGET_TS4800
|
||||
bool "Support TS4800"
|
||||
select MX51
|
||||
|
||||
config TARGET_USBARMORY
|
||||
bool "Support USB armory"
|
||||
select MX53
|
||||
@@ -83,12 +74,10 @@ config SYS_SOC
|
||||
|
||||
source "board/beckhoff/mx53cx9020/Kconfig"
|
||||
source "board/freescale/mx51evk/Kconfig"
|
||||
source "board/freescale/mx53evk/Kconfig"
|
||||
source "board/freescale/mx53loco/Kconfig"
|
||||
source "board/ge/mx53ppd/Kconfig"
|
||||
source "board/inversepath/usbarmory/Kconfig"
|
||||
source "board/k+p/kp_imx53/Kconfig"
|
||||
source "board/menlo/m53menlo/Kconfig"
|
||||
source "board/technologic/ts4800/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -111,12 +111,6 @@ choice
|
||||
prompt "MX6 board select"
|
||||
optional
|
||||
|
||||
config TARGET_ADVANTECH_DMS_BA16
|
||||
bool "Advantech dms-ba16"
|
||||
depends on MX6Q
|
||||
select BOARD_LATE_INIT
|
||||
imply CMD_SATA
|
||||
|
||||
config TARGET_APALIS_IMX6
|
||||
bool "Toradex Apalis iMX6 board"
|
||||
depends on MX6Q
|
||||
@@ -150,15 +144,6 @@ config TARGET_ARISTAINETOS2CCSLB
|
||||
imply CMD_SATA
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_CGTQMX6EVAL
|
||||
bool "cgtqmx6eval"
|
||||
depends on MX6QDL
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_CM_FX6
|
||||
bool "CM-FX6"
|
||||
depends on MX6QDL
|
||||
@@ -302,9 +287,6 @@ config TARGET_MX6MEMCAL
|
||||
and characterize the memory layout of a new design during the initial
|
||||
development and pre-production stages.
|
||||
|
||||
config TARGET_MX6QARM2
|
||||
bool "mx6qarm2"
|
||||
|
||||
config TARGET_MX6DL_MAMOJ
|
||||
bool "Support BTicino Mamoj"
|
||||
depends on MX6QDL
|
||||
@@ -476,11 +458,6 @@ config TARGET_OPOS6ULDEV
|
||||
depends on MX6UL
|
||||
select MX6UL_OPOS6UL
|
||||
|
||||
config TARGET_OT1200
|
||||
bool "Bachmann OT1200"
|
||||
select SUPPORT_SPL
|
||||
imply CMD_SATA
|
||||
|
||||
config TARGET_PICO_IMX6
|
||||
bool "PICO-IMX6"
|
||||
depends on MX6QDL
|
||||
@@ -504,14 +481,6 @@ config TARGET_LITEBOARD
|
||||
select BOARD_LATE_INIT
|
||||
select MX6UL_LITESOM
|
||||
|
||||
config TARGET_PLATINUM_PICON
|
||||
bool "platinum-picon"
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_PLATINUM_TITANIUM
|
||||
bool "platinum-titanium"
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_PCM058
|
||||
bool "Phytec PCM058 i.MX6 Quad"
|
||||
depends on MX6Q
|
||||
@@ -521,12 +490,6 @@ config TARGET_PCM058
|
||||
select OF_CONTROL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_PFLA02
|
||||
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
|
||||
depends on MX6QDL
|
||||
select BOARD_LATE_INIT
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_PCL063
|
||||
bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
|
||||
depends on MX6UL
|
||||
@@ -551,9 +514,6 @@ config TARGET_PCL063_ULL
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_SECOMX6
|
||||
bool "secomx6 boards"
|
||||
|
||||
config TARGET_SOMLABS_VISIONSOM_6ULL
|
||||
bool "visionsom-6ull"
|
||||
depends on MX6ULL
|
||||
@@ -570,10 +530,6 @@ config TARGET_TBS2910
|
||||
bool "TBS2910 Matrix ARM mini PC"
|
||||
depends on MX6Q
|
||||
|
||||
config TARGET_TITANIUM
|
||||
bool "titanium"
|
||||
depends on MX6Q
|
||||
|
||||
config TARGET_KP_IMX6Q_TPC
|
||||
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
|
||||
depends on MX6QDL
|
||||
@@ -645,31 +601,6 @@ config TARGET_WARP
|
||||
depends on MX6SL
|
||||
select BOARD_LATE_INIT
|
||||
|
||||
config TARGET_XPRESS
|
||||
bool "CCV xPress"
|
||||
depends on MX6UL
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_ZC5202
|
||||
bool "zc5202"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_ZC5601
|
||||
bool "zc5601"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_BRPPT2
|
||||
bool "brppt2"
|
||||
depends on MX6QDL
|
||||
@@ -695,23 +626,15 @@ config SYS_SOC
|
||||
|
||||
source "board/ge/bx50v3/Kconfig"
|
||||
source "board/ge/b1x5v2/Kconfig"
|
||||
source "board/advantech/dms-ba16/Kconfig"
|
||||
source "board/aristainetos/Kconfig"
|
||||
source "board/armadeus/opos6uldev/Kconfig"
|
||||
source "board/bachmann/ot1200/Kconfig"
|
||||
source "board/barco/platinum/Kconfig"
|
||||
source "board/barco/titanium/Kconfig"
|
||||
source "board/boundary/nitrogen6x/Kconfig"
|
||||
source "board/bticino/mamoj/Kconfig"
|
||||
source "board/ccv/xpress/Kconfig"
|
||||
source "board/compulab/cm_fx6/Kconfig"
|
||||
source "board/congatec/cgtqmx6eval/Kconfig"
|
||||
source "board/dhelectronics/dh_imx6/Kconfig"
|
||||
source "board/el/el6x/Kconfig"
|
||||
source "board/embest/mx6boards/Kconfig"
|
||||
source "board/engicam/imx6q/Kconfig"
|
||||
source "board/engicam/imx6ul/Kconfig"
|
||||
source "board/freescale/mx6qarm2/Kconfig"
|
||||
source "board/freescale/mx6memcal/Kconfig"
|
||||
source "board/freescale/mx6sabreauto/Kconfig"
|
||||
source "board/freescale/mx6sabresd/Kconfig"
|
||||
@@ -723,7 +646,6 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
|
||||
source "board/freescale/mx6ullevk/Kconfig"
|
||||
source "board/grinn/liteboard/Kconfig"
|
||||
source "board/phytec/pcm058/Kconfig"
|
||||
source "board/phytec/pfla02/Kconfig"
|
||||
source "board/phytec/pcl063/Kconfig"
|
||||
source "board/gateworks/gw_ventana/Kconfig"
|
||||
source "board/kosagi/novena/Kconfig"
|
||||
@@ -731,7 +653,6 @@ source "board/softing/vining_2000/Kconfig"
|
||||
source "board/liebherr/display5/Kconfig"
|
||||
source "board/liebherr/mccmon6/Kconfig"
|
||||
source "board/logicpd/imx6/Kconfig"
|
||||
source "board/seco/Kconfig"
|
||||
source "board/solidrun/mx6cuboxi/Kconfig"
|
||||
source "board/somlabs/visionsom-6ull/Kconfig"
|
||||
source "board/technexion/pico-imx6/Kconfig"
|
||||
|
||||
@@ -16,9 +16,6 @@ config TARGET_MX23EVK
|
||||
bool "Support mx23evk"
|
||||
select BOARD_EARLY_INIT_F
|
||||
|
||||
config TARGET_SANSA_FUZE_PLUS
|
||||
bool "Support sansa_fuze_plus"
|
||||
|
||||
config TARGET_XFI3
|
||||
bool "Support xfi3"
|
||||
|
||||
@@ -29,8 +26,6 @@ config SYS_SOC
|
||||
|
||||
source "board/olimex/mx23_olinuxino/Kconfig"
|
||||
source "board/freescale/mx23evk/Kconfig"
|
||||
source "board/sandisk/sansa_fuze_plus/Kconfig"
|
||||
source "board/creative/xfi3/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -51,12 +46,6 @@ config TARGET_MX28EVK
|
||||
bool "Support mx28evk"
|
||||
select BOARD_EARLY_INIT_F
|
||||
|
||||
config TARGET_SC_SPS_1
|
||||
bool "Support sc_sps_1"
|
||||
|
||||
config TARGET_TS4600
|
||||
bool "Support TS4600"
|
||||
|
||||
config TARGET_XEA
|
||||
bool "Support XEA"
|
||||
|
||||
@@ -68,7 +57,5 @@ config SYS_SOC
|
||||
source "board/freescale/mx28evk/Kconfig"
|
||||
source "board/liebherr/xea/Kconfig"
|
||||
source "board/ppcag/bg0900/Kconfig"
|
||||
source "board/schulercontrol/sc_sps_1/Kconfig"
|
||||
source "board/technologic/ts4600/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -74,8 +74,6 @@
|
||||
*/
|
||||
#ifdef CONFIG_IDE
|
||||
#define __io
|
||||
#define CONFIG_IDE_PREINIT
|
||||
#define CONFIG_MVSATA_IDE_USE_PORT1
|
||||
/* Needs byte-swapping for ATA data register */
|
||||
#define CONFIG_IDE_SWAP_IO
|
||||
/* Data, registers and alternate blocks are at the same offset */
|
||||
|
||||
@@ -89,18 +89,11 @@ config TARGET_OMAP3_OVERO
|
||||
select OMAP3_GPIO_6
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_AM3517_CRANE
|
||||
bool "am3517_crane"
|
||||
|
||||
config TARGET_OMAP3_PANDORA
|
||||
bool "OMAP3 Pandora"
|
||||
select OMAP3_GPIO_4
|
||||
select OMAP3_GPIO_6
|
||||
|
||||
config TARGET_TRICORDER
|
||||
bool "Tricorder"
|
||||
select OMAP3_GPIO_2
|
||||
|
||||
config TARGET_OMAP3_LOGIC
|
||||
bool "OMAP3 Logic"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -166,11 +159,8 @@ source "board/ti/beagle/Kconfig"
|
||||
source "board/timll/devkit8000/Kconfig"
|
||||
source "board/ti/evm/Kconfig"
|
||||
source "board/isee/igep00x0/Kconfig"
|
||||
source "board/ti/am3517crane/Kconfig"
|
||||
source "board/corscience/tricorder/Kconfig"
|
||||
source "board/logicpd/omap3som/Kconfig"
|
||||
source "board/nokia/rx51/Kconfig"
|
||||
source "board/technexion/tao3530/Kconfig"
|
||||
source "board/lg/sniper/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -10,9 +10,6 @@ config TARGET_OMAP4_PANDA
|
||||
config TARGET_OMAP4_SDP4430
|
||||
bool "TI OMAP4 SDP4430"
|
||||
|
||||
config TARGET_KC1
|
||||
bool "Amazon Kindle Fire (first generation)"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
@@ -20,6 +17,5 @@ config SYS_SOC
|
||||
|
||||
source "board/ti/panda/Kconfig"
|
||||
source "board/ti/sdp4430/Kconfig"
|
||||
source "board/amazon/kc1/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -28,11 +28,6 @@ config TARGET_CADDY2
|
||||
bool "Support caddy2"
|
||||
select ARCH_MPC8349
|
||||
|
||||
config TARGET_MPC8308RDB
|
||||
bool "Support MPC8308RDB"
|
||||
select ARCH_MPC8308
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
|
||||
config TARGET_MPC8313ERDB_NOR
|
||||
bool "Support MPC8313ERDB_NOR"
|
||||
select ARCH_MPC8313
|
||||
@@ -75,18 +70,6 @@ config TARGET_MPC8349EMDS_SDRAM
|
||||
select SYS_FSL_DDR_BE
|
||||
select SYS_FSL_HAS_DDR2
|
||||
|
||||
config TARGET_MPC8349ITX
|
||||
bool "Support MPC8349ITX"
|
||||
select ARCH_MPC8349
|
||||
imply CMD_IRQ
|
||||
|
||||
config TARGET_MPC837XEMDS
|
||||
bool "Support MPC837XEMDS"
|
||||
select ARCH_MPC837X
|
||||
select BOARD_EARLY_INIT_F
|
||||
imply CMD_SATA
|
||||
imply FSL_SATA
|
||||
|
||||
config TARGET_MPC837XERDB
|
||||
bool "Support MPC837XERDB"
|
||||
select ARCH_MPC837X
|
||||
@@ -142,16 +125,6 @@ config TARGET_TQM834X
|
||||
bool "Support TQM834x"
|
||||
select ARCH_MPC8349
|
||||
|
||||
config TARGET_HRCON
|
||||
bool "Support hrcon"
|
||||
select ARCH_MPC8308
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
|
||||
config TARGET_STRIDER
|
||||
bool "Support strider"
|
||||
select ARCH_MPC8308
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
imply CMD_PCA953X
|
||||
|
||||
config TARGET_GAZERBEAM
|
||||
bool "Support gazerbeam"
|
||||
@@ -330,14 +303,11 @@ config FSL_ELBC
|
||||
bool
|
||||
|
||||
source "board/esd/vme8349/Kconfig"
|
||||
source "board/freescale/mpc8308rdb/Kconfig"
|
||||
source "board/freescale/mpc8313erdb/Kconfig"
|
||||
source "board/freescale/mpc8315erdb/Kconfig"
|
||||
source "board/freescale/mpc8323erdb/Kconfig"
|
||||
source "board/freescale/mpc832xemds/Kconfig"
|
||||
source "board/freescale/mpc8349emds/Kconfig"
|
||||
source "board/freescale/mpc8349itx/Kconfig"
|
||||
source "board/freescale/mpc837xemds/Kconfig"
|
||||
source "board/freescale/mpc837xerdb/Kconfig"
|
||||
source "board/ids/ids8313/Kconfig"
|
||||
source "board/keymile/Kconfig"
|
||||
|
||||
@@ -210,14 +210,6 @@ config TARGET_T2080RDB
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_T2081QDS
|
||||
bool "Support T2081QDS"
|
||||
select ARCH_T2081
|
||||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
|
||||
select FSL_DDR_INTERACTIVE
|
||||
|
||||
config TARGET_T4160RDB
|
||||
bool "Support T4160RDB"
|
||||
select ARCH_T4160
|
||||
@@ -234,10 +226,6 @@ config TARGET_T4240RDB
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_CONTROLCENTERD
|
||||
bool "Support controlcenterd"
|
||||
select ARCH_P1022
|
||||
|
||||
config TARGET_KMP204X
|
||||
bool "Support kmp204x"
|
||||
select VENDOR_KM
|
||||
@@ -266,18 +254,6 @@ config TARGET_UCP1020
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_CYRUS_P5020
|
||||
bool "Support Varisys Cyrus P5020"
|
||||
select ARCH_P5020
|
||||
select PHYS_64BIT
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_CYRUS_P5040
|
||||
bool "Support Varisys Cyrus P5040"
|
||||
select ARCH_P5040
|
||||
select PHYS_64BIT
|
||||
imply PANIC_HANG
|
||||
|
||||
endchoice
|
||||
|
||||
config ARCH_B4420
|
||||
@@ -576,23 +552,6 @@ config ARCH_P1021
|
||||
imply CMD_REGINFO
|
||||
imply SATA_SIL
|
||||
|
||||
config ARCH_P1022
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_FSL_ERRATUM_A004477
|
||||
select SYS_FSL_ERRATUM_A004508
|
||||
select SYS_FSL_ERRATUM_A005125
|
||||
select SYS_FSL_ERRATUM_ELBC_A001
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
select SYS_FSL_ERRATUM_SATA_A001
|
||||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_2
|
||||
select SYS_PPC_E500_USE_DEBUG_TLB
|
||||
select FSL_ELBC
|
||||
|
||||
config ARCH_P1023
|
||||
bool
|
||||
select FSL_LAW
|
||||
@@ -756,31 +715,6 @@ config ARCH_P4080
|
||||
imply CMD_REGINFO
|
||||
imply SATA_SIL
|
||||
|
||||
config ARCH_P5020
|
||||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_DDR_VER_44
|
||||
select SYS_FSL_ERRATUM_A004510
|
||||
select SYS_FSL_ERRATUM_A005275
|
||||
select SYS_FSL_ERRATUM_A006261
|
||||
select SYS_FSL_ERRATUM_DDR_A003
|
||||
select SYS_FSL_ERRATUM_DDR_A003474
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
select SYS_FSL_ERRATUM_I2C_A004447
|
||||
select SYS_FSL_ERRATUM_SRIO_A004034
|
||||
select SYS_FSL_ERRATUM_USB14
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS1
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_PPC64
|
||||
select FSL_ELBC
|
||||
imply CMD_SATA
|
||||
imply CMD_REGINFO
|
||||
imply FSL_SATA
|
||||
|
||||
config ARCH_P5040
|
||||
bool
|
||||
select E500MC
|
||||
@@ -928,29 +862,6 @@ config ARCH_T2080
|
||||
imply CMD_REGINFO
|
||||
imply FSL_SATA
|
||||
|
||||
config ARCH_T2081
|
||||
bool
|
||||
select E500MC
|
||||
select E6500
|
||||
select FSL_LAW
|
||||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A006379
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
select SYS_FSL_ERRATUM_A007186
|
||||
select SYS_FSL_ERRATUM_A007212
|
||||
select SYS_FSL_ERRATUM_A009942
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_QORIQ_CHASSIS2
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_PPC64
|
||||
select FSL_IFC
|
||||
imply CMD_NAND
|
||||
imply CMD_REGINFO
|
||||
|
||||
config ARCH_T4160
|
||||
bool
|
||||
select E500MC
|
||||
@@ -1052,19 +963,16 @@ config MAX_CPUS
|
||||
ARCH_P5040 || \
|
||||
ARCH_T1040 || \
|
||||
ARCH_T1042 || \
|
||||
ARCH_T2080 || \
|
||||
ARCH_T2081
|
||||
ARCH_T2080
|
||||
default 2 if ARCH_B4420 || \
|
||||
ARCH_BSC9132 || \
|
||||
ARCH_MPC8572 || \
|
||||
ARCH_P1020 || \
|
||||
ARCH_P1021 || \
|
||||
ARCH_P1022 || \
|
||||
ARCH_P1023 || \
|
||||
ARCH_P1024 || \
|
||||
ARCH_P1025 || \
|
||||
ARCH_P2020 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_T1023 || \
|
||||
ARCH_T1024
|
||||
default 1
|
||||
@@ -1093,7 +1001,6 @@ config SYS_CCSRBAR_DEFAULT
|
||||
ARCH_P1011 || \
|
||||
ARCH_P1020 || \
|
||||
ARCH_P1021 || \
|
||||
ARCH_P1022 || \
|
||||
ARCH_P1024 || \
|
||||
ARCH_P1025 || \
|
||||
ARCH_P2020
|
||||
@@ -1103,14 +1010,12 @@ config SYS_CCSRBAR_DEFAULT
|
||||
ARCH_P2041 || \
|
||||
ARCH_P3041 || \
|
||||
ARCH_P4080 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_P5040 || \
|
||||
ARCH_T1023 || \
|
||||
ARCH_T1024 || \
|
||||
ARCH_T1040 || \
|
||||
ARCH_T1042 || \
|
||||
ARCH_T2080 || \
|
||||
ARCH_T2081 || \
|
||||
ARCH_T4160 || \
|
||||
ARCH_T4240
|
||||
default 0xe0000000 if ARCH_QEMU_E500
|
||||
@@ -1224,7 +1129,7 @@ config SYS_FSL_A004447_SVR_REV
|
||||
default 0x00 if ARCH_MPC8548
|
||||
default 0x10 if ARCH_P1010
|
||||
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
|
||||
default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
|
||||
default 0x20 if ARCH_P3041 || ARCH_P4080
|
||||
|
||||
config SYS_FSL_ERRATUM_IFC_A002769
|
||||
bool
|
||||
@@ -1294,10 +1199,8 @@ config SYS_FSL_NUM_LAWS
|
||||
ARCH_P2041 || \
|
||||
ARCH_P3041 || \
|
||||
ARCH_P4080 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_P5040 || \
|
||||
ARCH_T2080 || \
|
||||
ARCH_T2081 || \
|
||||
ARCH_T4160 || \
|
||||
ARCH_T4240
|
||||
default 16 if ARCH_T1023 || \
|
||||
@@ -1313,7 +1216,6 @@ config SYS_FSL_NUM_LAWS
|
||||
ARCH_P1011 || \
|
||||
ARCH_P1020 || \
|
||||
ARCH_P1021 || \
|
||||
ARCH_P1022 || \
|
||||
ARCH_P1023 || \
|
||||
ARCH_P1024 || \
|
||||
ARCH_P1025 || \
|
||||
@@ -1363,7 +1265,6 @@ config SYS_PPC_E500_DEBUG_TLB
|
||||
ARCH_P1011 || \
|
||||
ARCH_P1020 || \
|
||||
ARCH_P1021 || \
|
||||
ARCH_P1022 || \
|
||||
ARCH_P1024 || \
|
||||
ARCH_P1025 || \
|
||||
ARCH_P2020
|
||||
@@ -1404,7 +1305,6 @@ config SYS_FSL_LBC_CLK_DIV
|
||||
default 2 if ARCH_P2041 || \
|
||||
ARCH_P3041 || \
|
||||
ARCH_P4080 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_P5040
|
||||
default 1
|
||||
|
||||
@@ -1429,11 +1329,9 @@ source "board/freescale/t104xrdb/Kconfig"
|
||||
source "board/freescale/t208xqds/Kconfig"
|
||||
source "board/freescale/t208xrdb/Kconfig"
|
||||
source "board/freescale/t4rdb/Kconfig"
|
||||
source "board/gdsys/p1022/Kconfig"
|
||||
source "board/keymile/Kconfig"
|
||||
source "board/sbc8548/Kconfig"
|
||||
source "board/socrates/Kconfig"
|
||||
source "board/varisys/cyrus/Kconfig"
|
||||
source "board/xes/xpedite520x/Kconfig"
|
||||
source "board/xes/xpedite537x/Kconfig"
|
||||
source "board/xes/xpedite550x/Kconfig"
|
||||
|
||||
@@ -40,7 +40,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
|
||||
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
|
||||
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
|
||||
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
|
||||
obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
|
||||
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
|
||||
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
|
||||
obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
|
||||
@@ -51,7 +50,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
|
||||
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
|
||||
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
|
||||
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
|
||||
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
|
||||
|
||||
|
||||
obj-$(CONFIG_QE) += qe_io.o
|
||||
@@ -70,7 +68,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
|
||||
@@ -78,7 +75,6 @@ obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
|
||||
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
|
||||
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
|
||||
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
|
||||
obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
|
||||
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
|
||||
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
|
||||
obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
|
||||
@@ -90,7 +86,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
|
||||
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
|
||||
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
|
||||
@@ -1,129 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
* Author: Timur Tabi <timur@freescale.com>
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <log.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
#define SRDS1_MAX_LANES 4
|
||||
#define SRDS2_MAX_LANES 2
|
||||
|
||||
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
|
||||
|
||||
static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
|
||||
[0x00] = {NONE, NONE, NONE, NONE},
|
||||
[0x01] = {NONE, NONE, NONE, NONE},
|
||||
[0x02] = {NONE, NONE, NONE, NONE},
|
||||
[0x03] = {NONE, NONE, NONE, NONE},
|
||||
[0x04] = {NONE, NONE, NONE, NONE},
|
||||
[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
|
||||
[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
|
||||
[0x09] = {PCIE1, NONE, NONE, NONE},
|
||||
[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
|
||||
[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
|
||||
[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
|
||||
[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
||||
[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
|
||||
};
|
||||
|
||||
static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
|
||||
[0x00] = {PCIE3, PCIE3},
|
||||
[0x01] = {PCIE2, PCIE3},
|
||||
[0x02] = {SATA1, SATA2},
|
||||
[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x04] = {NONE, NONE},
|
||||
[0x06] = {SATA1, SATA2},
|
||||
[0x07] = {NONE, NONE},
|
||||
[0x09] = {PCIE3, PCIE2},
|
||||
[0x0a] = {SATA1, SATA2},
|
||||
[0x0b] = {NONE, NONE},
|
||||
[0x0d] = {PCIE3, PCIE2},
|
||||
[0x0e] = {SATA1, SATA2},
|
||||
[0x0f] = {NONE, NONE},
|
||||
[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x16] = {SATA1, SATA2},
|
||||
[0x17] = {NONE, NONE},
|
||||
[0x18] = {PCIE3, PCIE3},
|
||||
[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x1a] = {SATA1, SATA2},
|
||||
[0x1b] = {NONE, NONE},
|
||||
[0x1c] = {PCIE3, PCIE3},
|
||||
[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x1e] = {SATA1, SATA2},
|
||||
[0x1f] = {NONE, NONE},
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!(serdes1_prtcl_map & (1 << NONE)))
|
||||
fsl_serdes_init();
|
||||
|
||||
ret = (1 << device) & serdes1_prtcl_map;
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(serdes2_prtcl_map & (1 << NONE)))
|
||||
fsl_serdes_init();
|
||||
|
||||
return (1 << device) & serdes2_prtcl_map;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
int lane;
|
||||
|
||||
if (serdes1_prtcl_map & (1 << NONE) &&
|
||||
serdes2_prtcl_map & (1 << NONE))
|
||||
return;
|
||||
|
||||
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
|
||||
|
||||
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
||||
return;
|
||||
}
|
||||
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
|
||||
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
|
||||
serdes1_prtcl_map |= (1 << lane_prtcl);
|
||||
}
|
||||
|
||||
/* Set the first bit to indicate serdes has been initialized */
|
||||
serdes1_prtcl_map |= (1 << NONE);
|
||||
|
||||
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
||||
return;
|
||||
}
|
||||
|
||||
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
|
||||
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
|
||||
serdes2_prtcl_map |= (1 << lane_prtcl);
|
||||
}
|
||||
|
||||
/* Set the first bit to indicate serdes has been initialized */
|
||||
serdes2_prtcl_map |= (1 << NONE);
|
||||
}
|
||||
@@ -1,124 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
|
||||
/* dqrr liodn, frame data liodn, liodn off, sdest */
|
||||
SET_QP_INFO(1, 2, 1, 0),
|
||||
SET_QP_INFO(3, 4, 2, 1),
|
||||
SET_QP_INFO(5, 6, 3, 0),
|
||||
SET_QP_INFO(7, 8, 4, 1),
|
||||
SET_QP_INFO(9, 10, 5, 0),
|
||||
SET_QP_INFO(11, 12, 6, 1),
|
||||
SET_QP_INFO(13, 14, 7, 0),
|
||||
SET_QP_INFO(15, 16, 8, 1),
|
||||
SET_QP_INFO(17, 18, 9, 0),
|
||||
SET_QP_INFO(19, 20, 10, 1),
|
||||
};
|
||||
#endif
|
||||
|
||||
struct srio_liodn_id_table srio_liodn_tbl[] = {
|
||||
SET_SRIO_LIODN_2(1, 199, 200),
|
||||
SET_SRIO_LIODN_2(2, 201, 202),
|
||||
};
|
||||
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
|
||||
|
||||
struct liodn_id_table liodn_tbl[] = {
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
SET_QMAN_LIODN(31),
|
||||
SET_BMAN_LIODN(32),
|
||||
#endif
|
||||
|
||||
SET_SDHC_LIODN(1, 64),
|
||||
|
||||
SET_PME_LIODN(117),
|
||||
|
||||
SET_USB_LIODN(1, "fsl-usb2-mph", 125),
|
||||
SET_USB_LIODN(2, "fsl-usb2-dr", 126),
|
||||
|
||||
SET_SATA_LIODN(1, 127),
|
||||
SET_SATA_LIODN(2, 128),
|
||||
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
|
||||
|
||||
SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
|
||||
SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
|
||||
|
||||
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
|
||||
};
|
||||
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
struct fman_liodn_id_table fman1_liodn_tbl[] = {
|
||||
SET_FMAN_RX_1G_LIODN(1, 0, 10),
|
||||
SET_FMAN_RX_1G_LIODN(1, 1, 11),
|
||||
SET_FMAN_RX_1G_LIODN(1, 2, 12),
|
||||
SET_FMAN_RX_1G_LIODN(1, 3, 13),
|
||||
SET_FMAN_RX_1G_LIODN(1, 4, 14),
|
||||
SET_FMAN_RX_10G_LIODN(1, 0, 15),
|
||||
};
|
||||
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
|
||||
#endif
|
||||
|
||||
struct liodn_id_table sec_liodn_tbl[] = {
|
||||
SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
|
||||
SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
|
||||
SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
|
||||
SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(a, 154),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(b, 155),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(c, 156),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(d, 157),
|
||||
SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
|
||||
SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
|
||||
};
|
||||
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
|
||||
struct liodn_id_table raide_liodn_tbl[] = {
|
||||
SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
|
||||
SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
|
||||
SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
|
||||
SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
|
||||
};
|
||||
int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_RMAN
|
||||
struct liodn_id_table rman_liodn_tbl[] = {
|
||||
/* Set RMan block 0-3 liodn offset */
|
||||
SET_RMAN_LIODN(0, 6),
|
||||
SET_RMAN_LIODN(1, 7),
|
||||
SET_RMAN_LIODN(2, 8),
|
||||
SET_RMAN_LIODN(3, 9),
|
||||
};
|
||||
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
|
||||
#endif
|
||||
|
||||
struct liodn_id_table liodn_bases[] = {
|
||||
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_PME
|
||||
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
|
||||
[FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_RMAN
|
||||
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
|
||||
#endif
|
||||
};
|
||||
@@ -1,134 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include "fsl_corenet_serdes.h"
|
||||
|
||||
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
|
||||
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
|
||||
[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
|
||||
PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
|
||||
XAUI_FM1, XAUI_FM1, },
|
||||
[0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4, },
|
||||
[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
|
||||
SRIO1, },
|
||||
[0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
|
||||
NONE, NONE, },
|
||||
[0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
|
||||
SATA1, SATA2, },
|
||||
[0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
|
||||
XAUI_FM1, XAUI_FM1, },
|
||||
[0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4, },
|
||||
[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
|
||||
NONE, NONE, },
|
||||
[0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
|
||||
[0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
|
||||
NONE, NONE, },
|
||||
[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
|
||||
XAUI_FM1, XAUI_FM1, },
|
||||
[0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
|
||||
NONE, NONE, },
|
||||
[0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
|
||||
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
||||
NONE, NONE, SATA1, SATA2, },
|
||||
[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
|
||||
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
|
||||
NONE, SATA1, SATA2, },
|
||||
[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
|
||||
XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
|
||||
[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
|
||||
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
|
||||
NONE, SATA1, SATA2, },
|
||||
[0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
|
||||
XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
|
||||
{
|
||||
if (!serdes_lane_enabled(lane))
|
||||
return NONE;
|
||||
|
||||
return serdes_cfg_tbl[cfg][lane];
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(u32 prtcl) {
|
||||
int i;
|
||||
|
||||
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (serdes_cfg_tbl[prtcl][i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info)
|
||||
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
|
||||
*/
|
||||
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
|
||||
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
defined(CONFIG_ARCH_T2080)
|
||||
svr = get_svr();
|
||||
switch (SVR_SOC_VER(svr)) {
|
||||
case SVR_T4240:
|
||||
@@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
|
||||
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
defined(CONFIG_ARCH_T2080)
|
||||
#define FM1_CLK_SEL 0xe0000000
|
||||
#define FM1_CLK_SHIFT 29
|
||||
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
||||
@@ -608,8 +608,7 @@ int get_clocks(void)
|
||||
* AN2919.
|
||||
*/
|
||||
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
|
||||
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
|
||||
defined(CONFIG_ARCH_P1022)
|
||||
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
|
||||
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
||||
#elif defined(CONFIG_ARCH_MPC8544)
|
||||
/*
|
||||
|
||||
@@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
{}
|
||||
};
|
||||
|
||||
#ifndef CONFIG_ARCH_T2081
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
@@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
#ifndef CONFIG_ARCH_T2081
|
||||
serdes2_cfg_tbl,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
|
||||
@@ -66,10 +66,6 @@
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_P1022)
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_P1023)
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 2
|
||||
@@ -157,24 +153,6 @@
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P5040)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
@@ -364,7 +342,7 @@
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#elif defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
@@ -381,9 +359,6 @@
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#elif defined(CONFIG_ARCH_T2081)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#endif
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_PME_PLAT_CLK_DIV 1
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
defined(CONFIG_TARGET_T4240QDS) || \
|
||||
defined(CONFIG_TARGET_T2080QDS) || \
|
||||
defined(CONFIG_TARGET_T2080RDB) || \
|
||||
defined(CONFIG_TARGET_T1040QDS) || \
|
||||
defined(CONFIG_TARGET_T1040RDB) || \
|
||||
defined(CONFIG_TARGET_T1040D4RDB) || \
|
||||
defined(CONFIG_TARGET_T1042RDB) || \
|
||||
@@ -58,7 +57,6 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_P3041) || \
|
||||
defined(CONFIG_ARCH_P4080) || \
|
||||
defined(CONFIG_ARCH_P5020) || \
|
||||
defined(CONFIG_ARCH_P5040) || \
|
||||
defined(CONFIG_ARCH_P2041)
|
||||
#define CONFIG_FSL_TRUST_ARCH_v1
|
||||
|
||||
@@ -1808,7 +1808,7 @@ typedef struct ccsr_gur {
|
||||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#elif defined(CONFIG_ARCH_T2080)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
@@ -1853,7 +1853,7 @@ typedef struct ccsr_gur {
|
||||
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_P2041) || \
|
||||
defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
|
||||
defined(CONFIG_ARCH_P3041)
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
|
||||
@@ -1880,7 +1880,7 @@ typedef struct ccsr_gur {
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
|
||||
@@ -2157,10 +2157,7 @@ typedef struct ccsr_gur {
|
||||
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
|
||||
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
|
||||
#define MPC85xx_PORDEVSR_PCI1 0x00800000
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
|
||||
#elif defined(CONFIG_ARCH_P1023)
|
||||
#if defined(CONFIG_ARCH_P1023)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
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||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
|
||||
#else
|
||||
@@ -2278,12 +2275,6 @@ typedef struct ccsr_gur {
|
||||
#define MPC85xx_PMUXCR_QE11 0x00000010
|
||||
#define MPC85xx_PMUXCR_QE12 0x00000008
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
|
||||
#define MPC85xx_PMUXCR_TDM 0x00014800
|
||||
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
|
||||
#define MPC85xx_PMUXCR_SPI 0x00000000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
|
||||
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
|
||||
@@ -2363,10 +2354,6 @@ typedef struct ccsr_gur {
|
||||
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
|
||||
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
|
||||
#define MPC85xx_PMUXCR2_USB 0x00150000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
|
||||
|
||||
Reference in New Issue
Block a user