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Merge https://source.denx.de/u-boot/custodians/u-boot-x86

Browse Source 
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
This commit is contained in:
Tom Rini 2021-08-02 21:35:50 -04:00
commit 3b64774323
37 changed files with 120 additions and 135 deletions
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21
Kconfig
View File

@ -343,27 +343,6 @@ config HAS_ROM
Enables building of a u-boot.rom target. This collects U-Boot and
any necessary binary blobs.
config ROM_NEEDS_BLOBS
bool
depends on HAS_ROM
help
Enable this if building the u-boot.rom target needs binary blobs, and
so cannot be done normally. In this case, U-Boot will only build the
ROM if the required blobs exist. If not, you will see an warning like:
Image 'main-section' is missing external blobs and is non-functional:
intel-descriptor intel-me intel-refcode intel-vga intel-mrc
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
depends on HAS_ROM
default y if !ROM_NEEDS_BLOBS
help
This option allows to build a ROM version of U-Boot.
The build process generally requires several binary blobs
which are not shipped in the U-Boot source tree.
Please, see doc/arch/x86.rst for details.
config SPL_IMAGE
string "SPL image used in the combined SPL+U-Boot image"
default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT

2
arch/x86/Kconfig
View File

@ -364,7 +364,6 @@ config HAVE_FSP
depends on !EFI
select USE_HOB
select HAS_ROM
select ROM_NEEDS_BLOBS
help
Select this option to add an Firmware Support Package binary to
the resulting U-Boot image. It is a binary blob which U-Boot uses
@ -525,7 +524,6 @@ config ENABLE_MRC_CACHE
config HAVE_MRC
bool "Add a System Agent binary"
select HAS_ROM
select ROM_NEEDS_BLOBS
depends on !HAVE_FSP
help
Select this option to add a System Agent binary to

13
arch/x86/cpu/mtrr.c
View File

@ -26,6 +26,7 @@
#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <linux/log2.h>
DECLARE_GLOBAL_DATA_PTR;
@ -155,12 +156,8 @@ int mtrr_commit(bool do_caches)
debug("open done\n");
qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
set_var_mtrr(i, req->type, req->start, req->size);
mtrr_set_next_var(req->type, req->start, req->size);
/* Clear the ones that are unused */
debug("clear\n");
for (; i < mtrr_get_var_count(); i++)
wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
debug("close\n");
mtrr_close(&state, do_caches);
debug("mtrr done\n");
@ -183,6 +180,9 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size)
if (!gd->arch.has_mtrr)
return -ENOSYS;
if (!is_power_of_2(size))
return -EINVAL;
if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
return -ENOSPC;
req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
@ -227,6 +227,9 @@ int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
{
int mtrr;
if (!is_power_of_2(size))
return -EINVAL;
mtrr = get_free_var_mtrr();
if (mtrr < 0)
return mtrr;

5
arch/x86/cpu/quark/Kconfig
View File

@ -24,7 +24,6 @@ if INTEL_QUARK
config HAVE_RMU
bool "Add a Remote Management Unit (RMU) binary"
select ROM_NEEDS_BLOBS
help
Select this option to add a Remote Management Unit (RMU) binary
to the resulting U-Boot image. It is a data block (up to 64K) of
@ -131,8 +130,8 @@ config SYS_CAR_SIZE
Space in bytes in eSRAM used as Cache-As-ARM (CAR).
Note this size must not exceed eSRAM's total size.
config X86_TSC_TIMER_EARLY_FREQ
config X86_TSC_TIMER_FREQ
int
default 400
default 400000000
endif

20
arch/x86/cpu/queensbay/tnc.c
View File

@ -18,19 +18,17 @@
static int __maybe_unused disable_igd(void)
{
struct udevice *igd, *sdvo;
struct udevice *igd = NULL;
struct udevice *sdvo = NULL;
int ret;
ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
if (ret)
return ret;
if (!igd)
return 0;
ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
if (ret)
return ret;
if (!sdvo)
/*
* In case the IGD and SDVO devices were already in disabled state,
* we should return and not proceed any further.
*/
dm_pci_bus_find_bdf(TNC_IGD, &igd);
dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
if (!igd || !sdvo)
return 0;
/*

4
arch/x86/cpu/tangier/acpi.c
View File

@ -89,8 +89,8 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
si->mmio_base_low = 0xff192000;
si->mmio_base_high = 0;
si->gsi_interrupt = 32;
si->interrupt_polarity = 1;
si->interrupt_mode = 0;
si->interrupt_polarity = 0; /* Active High */
si->interrupt_mode = 0; /* Level triggered */
si->num_channels = 8;
si->dma_address_width = 32;
si->base_request_line = 0;

3
arch/x86/dts/bayleybay.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -176,6 +176,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64dw",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

3
arch/x86/dts/baytrail_som-db5800-som-6867.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -200,6 +200,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "macronix,mx25l6405d",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

3
arch/x86/dts/cherryhill.dts
View File

@ -12,8 +12,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -149,6 +149,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "macronix,mx25u6435f", "jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {

4
arch/x86/dts/chromebook_coral.dts
View File

@ -8,7 +8,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
@ -362,6 +363,7 @@
u-boot,dm-pre-proper;
u-boot,dm-spl;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q128fw",
"jedec,spi-nor";
rw-mrc-cache {

3
arch/x86/dts/chromebook_link.dts
View File

@ -9,8 +9,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -430,6 +430,7 @@
#address-cells = <1>;
u-boot,dm-pre-reloc;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

3
arch/x86/dts/chromebook_samus.dts
View File

@ -7,8 +7,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
@ -594,6 +594,7 @@
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

3
arch/x86/dts/chromebox_panther.dts
View File

@ -4,8 +4,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -48,6 +48,7 @@
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

3
arch/x86/dts/conga-qeval20-qa3-e3845.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -187,6 +187,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "stmicro,n25q064a",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

7
arch/x86/dts/coreboot.dts
View File

@ -12,7 +12,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
@ -30,10 +31,6 @@
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;

3
arch/x86/dts/cougarcanyon2.dts
View File

@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -156,6 +156,7 @@
spi-flash@0 {
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64bv", "jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;
};

2
arch/x86/dts/crownbay.dts
View File

@ -13,8 +13,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

1
arch/x86/dts/dfi-bt700.dtsi
View File

@ -198,6 +198,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "stmicro,n25q064a",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

2
arch/x86/dts/edison.dts
View File

@ -10,8 +10,8 @@
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

7
arch/x86/dts/efi-x86_app.dts
View File

@ -6,7 +6,8 @@
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Application";
@ -16,10 +17,6 @@
stdout-path = &serial;
};
tsc-timer {
clock-frequency = <1000000000>;
};
serial: serial {
compatible = "efi,uart";
};

7
arch/x86/dts/efi-x86_payload.dts
View File

@ -12,7 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Payload";
@ -30,10 +31,6 @@
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;

7
arch/x86/dts/galileo.dts
View File

@ -11,7 +11,8 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
@ -41,10 +42,6 @@
};
};
tsc-timer {
clock-frequency = <400000000>;
};
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;

3
arch/x86/dts/minnowmax.dts
View File

@ -13,8 +13,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -200,6 +200,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
compatible = "stmicro,n25q064a",
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;

6
arch/x86/dts/qemu-x86_i440fx.dts
View File

@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -42,10 +42,6 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

6
arch/x86/dts/qemu-x86_q35.dts
View File

@ -22,8 +22,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -53,10 +53,6 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

2
arch/x86/dts/slimbootloader.dts
View File

@ -7,7 +7,7 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "slimbootloader x86 payload";

1
arch/x86/dts/tsc_timer.dtsi
View File

@ -1,6 +1,7 @@
/ {
tsc-timer {
compatible = "x86,tsc-timer";
clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
u-boot,dm-pre-reloc;
};
};

7
arch/x86/include/asm/mtrr.h
View File

@ -119,7 +119,7 @@ void mtrr_close(struct mtrr_state *state, bool do_caches);
*
* @type: Requested type (MTRR_TYPE_)
* @start: Start address
* @size: Size
* @size: Size, must be power of 2
*
* @return: 0 on success, non-zero on failure
*/
@ -144,8 +144,9 @@ int mtrr_commit(bool do_caches);
*
* @type: Requested type (MTRR_TYPE_)
* @start: Start address
* @size: Size
* @return 0 on success, -ENOSPC if there are no more MTRRs
* @size: Size, must be power of 2
* @return 0 on success, -EINVAL if size is not power of 2,
* -ENOSPC if there are no more MTRRs
*/
int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);

16
arch/x86/lib/fsp/fsp_common.c
View File

@ -61,22 +61,6 @@ void board_final_init(void)
debug("OK\n");
}
void board_final_cleanup(void)
{
u32 status;
/* TODO(sjg@chromium.org): This causes Linux to crash */
return;
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
}
int fsp_save_s3_stack(void)
{
struct udevice *dev;

27
arch/x86/lib/fsp/fsp_dram.c
View File

@ -48,12 +48,28 @@ int dram_init_banksize(void)
phys_addr_t mtrr_top;
phys_addr_t low_end;
uint bank;
bool update_mtrr;
/*
* For FSP1, the system memory and reserved memory used by FSP are
* already programmed in the MTRR by FSP. Also it is observed that
* FSP on Intel Queensbay platform reports the TSEG memory range
* that has the same RES_MEM_RESERVED resource type whose address
* is programmed by FSP to be near the top of 4 GiB space, which is
* not what we want for DRAM.
*
* However it seems FSP2's behavior is different. We need to add the
* DRAM range in MTRR otherwise the boot process goes very slowly,
* which was observed on Chrromebook Coral with FSP2.
*/
update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
if (!ll_boot_init()) {
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
return 0;
}
@ -76,8 +92,10 @@ int dram_init_banksize(void)
} else {
gd->bd->bi_dram[bank].start = res_desc->phys_start;
gd->bd->bi_dram[bank].size = res_desc->len;
mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
res_desc->len);
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK,
res_desc->phys_start,
res_desc->len);
log_debug("ram %llx %llx\n",
gd->bd->bi_dram[bank].start,
gd->bd->bi_dram[bank].size);
@ -92,7 +110,8 @@ int dram_init_banksize(void)
* Set up an MTRR to the top of low, reserved memory. This is necessary
* for graphics to run at full speed in U-Boot.
*/
mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
return 0;
}

17
arch/x86/lib/fsp2/fsp_common.c
View File

@ -6,8 +6,25 @@
#include <common.h>
#include <init.h>
#include <asm/fsp/fsp_support.h>
int arch_fsp_init(void)
{
return 0;
}
void board_final_cleanup(void)
{
u32 status;
/* TODO(sjg@chromium.org): This causes Linux to crash */
return;
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
}

9
cmd/x86/hob.c
View File

@ -78,7 +78,7 @@ static void show_hob_details(const struct hob_header *hdr)
const struct hob_res_desc *res = ptr;
const char *typename;
typename = res->type > 0 && res->type <= RES_MAX_MEM_TYPE ?
typename = res->type >= RES_SYS_MEM && res->type <= RES_MAX_MEM_TYPE ?
res_type[res->type] : "unknown";
printf(" base = %08llx, len = %08llx, end = %08llx, type = %d (%s)\n\n",
@ -158,8 +158,7 @@ static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
}
U_BOOT_CMD(hob, 3, 1, do_hob,
"[-v] [seq] Print Hand-Off Block (HOB) information"
" -v - Show detailed HOB information where available"
" seq - Record # to show (all by default)",
""
"[-v] [seq] Print Hand-Off Block (HOB) information",
" -v - Show detailed HOB information where available\n"
" seq - Record # to show (all by default)"
);

3
configs/crownbay_defconfig
View File

@ -8,8 +8,8 @@ CONFIG_MAX_CPUS=2
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_CROWNBAY=y
CONFIG_DISABLE_IGD=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
@ -46,6 +46,7 @@ CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_E1000=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y

13
doc/arch/x86.rst
View File

@ -42,17 +42,8 @@ Build Instructions for U-Boot as BIOS replacement (bare mode)
-------------------------------------------------------------
Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
little bit tricky, as generally it requires several binary blobs which are not
shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
not turned on by default in the U-Boot source tree. Firstly, you need turn it
on by enabling the ROM build either via an environment variable::
$ export BUILD_ROM=y
or via configuration::
CONFIG_BUILD_ROM=y
Both tell the Makefile to build u-boot.rom as a target.
shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build may
print some warnings if required binary blobs (e.g.: FSP) are not present.
CPU Microcode
-------------

6
drivers/spi/ich.c
View File

@ -918,12 +918,14 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
struct spi_slave *slave = dev_get_parent_priv(dev);
/*
* Yes this controller can only write a small number of bytes at
* Yes this controller can only transfer a small number of bytes at
* once! The limit is typically 64 bytes. For hardware sequencing a
* a loop is used to get around this.
*/
if (!plat->hwseq)
if (!plat->hwseq) {
slave->max_read_size = priv->databytes;
slave->max_write_size = priv->databytes;
}
/*
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash

8
drivers/timer/Kconfig
View File

@ -124,12 +124,12 @@ config RENESAS_OSTM_TIMER
Enables support for the Renesas OSTM Timer driver.
This timer is present on Renesas RZ/A1 R7S72100 SoCs.
config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
config X86_TSC_TIMER_FREQ
int "x86 TSC timer frequency in Hz"
depends on X86_TSC_TIMER
default 1000
default 1000000000
help
Sets the estimated CPU frequency in MHz when TSC is used as the
Sets the estimated CPU frequency in Hz when TSC is used as the
early timer and the frequency can neither be calibrated via some
hardware ways, nor got from device tree at the time when device
tree is not available yet.

5
drivers/timer/tsc_timer.c
View File

@ -425,12 +425,13 @@ static void tsc_timer_ensure_setup(bool early)
goto done;
if (early)
fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
else
return;
done:
gd->arch.clock_rate = fast_calibrate * 1000000;
if (!gd->arch.clock_rate)
gd->arch.clock_rate = fast_calibrate * 1000000;
}
gd->arch.tsc_inited = true;
}