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Merge with /home/m8/git/u-boot

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This commit is contained in:
Wolfgang Denk 2006-06-30 19:32:25 +02:00
commit 3b5f61a025
33 changed files with 5838 additions and 2044 deletions
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8
CHANGELOG
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@ -2,6 +2,10 @@
Changes since U-Boot 1.1.4:
======================================================================
* Fix CONFIG_440_GX define usage.
* Remove autogenerated bmp_logo.h file.
* Cleanup trab board for GCC-4.x
* VoiceBlue update: use new MTD flash partitioning methods, use more
@ -727,6 +731,10 @@ Changes since U-Boot 1.1.4:
Changes for U-Boot 1.1.4:
======================================================================
* Add support for AMCC 440SPe CPU based eval board (Yucca).
* Call serial_initialize() before first debug() is used.
* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
- Changed GPIO setup to enable another address line in order to
address 64M of FLASH.

6
MAKEALL
View File

@ -72,10 +72,10 @@ LIST_4xx=" \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 pcs440ep \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
PIP405 PLU405 PMC405 PPChameleonEVB \
sbc405 VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite \
yellowstone yosemite yucca \
"
#########################################################################

4
Makefile
View File

@ -981,6 +981,9 @@ yosemite_config: unconfig
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
yucca_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
#########################################################################
## MPC8220 Systems
#########################################################################
@ -1968,6 +1971,7 @@ clean:
rm -f board/netstar/*.srec board/netstar/*.bin
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
rm -f include/bmp_logo.h
clobber: clean
find . -type f \( -name .depend \

47
board/amcc/yucca/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o cmd_yucca.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend *~
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

288
board/amcc/yucca/cmd_yucca.c Normal file
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@ -0,0 +1,288 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* hacked for evb440spe
*/
#include <common.h>
#include <command.h>
#include "yucca.h"
#include <i2c.h>
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
/* ------------------------------------------------------------------------- */
int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
return setBootStrapClock (cmdtp, 1, flag, argc, argv);
}
/* ------------------------------------------------------------------------- */
/* Modify memory.
*
* Syntax:
* evb440spe wrclk prom0,prom1
*/
static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
int argc, char *argv[])
{
uchar chip;
ulong data;
int nbytes;
extern char console_buffer[];
char sysClock[4];
char cpuClock[4];
char plbClock[4];
char pcixClock[4];
if (argc < 3) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;
else
chip = IIC0_ALT_BOOTPROM_ADDR;
do {
printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0))
nbytes=0;
strcpy(sysClock, console_buffer);
} while (nbytes == 0);
do {
if (strcmp(sysClock, "66") == 0) {
printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
} else {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
}
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
} else {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "500") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
}
strcpy(cpuClock, console_buffer);
} while (nbytes == 0);
if (strcmp(cpuClock, "500") == 0){
strcpy(plbClock, "166");
} else if (strcmp(cpuClock, "533") == 0){
strcpy(plbClock, "133");
} else {
do {
if (strcmp(cpuClock, "400") == 0)
printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0)
printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
#endif
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
#endif
strcpy(plbClock, console_buffer);
} while (nbytes == 0);
}
do {
printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0) &
(strcmp(console_buffer, "100") != 0) &
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
strcpy(pcixClock, console_buffer);
} while (nbytes == 0);
printf("\nsys clk = %sMhz\n", sysClock);
printf("cpu clk = %sMhz\n", cpuClock);
printf("plb clk = %sMhz\n", plbClock);
printf("Pci-X clk = %sMhz\n", pcixClock);
do {
printf("\npress [y] to write I2C bootstrap \n");
printf("or [n] to abort. \n");
printf("Don't forget to set board switches \n");
printf("according to your choice before re-starting \n");
printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "n") == 0)
return 0;
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
if ((strcmp(cpuClock, "500") == 0))
data = 0x8778f2c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x84706206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x847062c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x85708206;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8570a256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x8570a206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x00000701;
if (strcmp(pcixClock, "66") == 0)
data = 0x00000601;
if (strcmp(pcixClock, "100") == 0)
data = 0x00000501;
if (strcmp(pcixClock, "133") == 0)
data = 0x00000401;
if (strcmp(plbClock, "166") == 0)
data = data | 0x05950000;
else
data = data | 0x05A50000;
#ifdef DEBUG
printf(" pin strap1 to write in i2c = %x\n", data);
#endif /* DEBUG */
udelay(1000);
if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap1 in %s\n", argv[2]);
return 0;
}
U_BOOT_CMD(
evb440spe, 3, 1, do_evb440spe,
"evb440spe - program the serial device strap\n",
"wrclk [prom0|prom1] - program the serial device strap\n"
);

42
board/amcc/yucca/config.mk Normal file
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@ -0,0 +1,42 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440SPe Reference Platform (yucca) board
#
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xfffb0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

1054
board/amcc/yucca/flash.c Normal file
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File diff suppressed because it is too large Load Diff

105
board/amcc/yucca/init.S Normal file
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@ -0,0 +1,105 @@
/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
#define TLB2(a) ((a) & 0x00000fbf)
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ;\
0: mflr r0 ;\
mtlr r1 ;\
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

157
board/amcc/yucca/u-boot.lds Normal file
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@ -0,0 +1,157 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

146
board/amcc/yucca/u-boot.lds.debug Normal file
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@ -0,0 +1,146 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1100
board/amcc/yucca/yucca.c Normal file
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File diff suppressed because it is too large Load Diff

363
board/amcc/yucca/yucca.h Normal file
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@ -0,0 +1,363 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __YUCCA_H_
#define __YUCCA_H_
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define TMR_FREQ_EXT 25000000
#define BOARD_UART_CLOCK 11059200
#define BOARD_OPTION_SELECTED 1
#define BOARD_OPTION_NOT_SELECTED 0
#define ENGINEERING_CLOCK_CHECKING "clk_chk"
#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
#define ENGINEERING_CLOCK_CHECKING_DATA 1
#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
/* ethernet definition */
#define MAX_ENETMODE_PARM 3
#define ENETMODE_NEG 0
#define ENETMODE_SPEED 1
#define ENETMODE_DUPLEX 2
#define ENETMODE_AUTONEG 0
#define ENETMODE_NO_AUTONEG 1
#define ENETMODE_10 2
#define ENETMODE_100 3
#define ENETMODE_1000 4
#define ENETMODE_HALF 5
#define ENETMODE_FULL 6
#define NUM_TLB_ENTRIES 64
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#define TLB_256MB_ALIGN_MASK 0xF0000000
#define TLB_16MB_ALIGN_MASK 0xFF000000
#define TLB_1MB_ALIGN_MASK 0xFFF00000
#define TLB_256KB_ALIGN_MASK 0xFFFC0000
#define TLB_64KB_ALIGN_MASK 0xFFFF0000
#define TLB_16KB_ALIGN_MASK 0xFFFFC000
#define TLB_4KB_ALIGN_MASK 0xFFFFF000
#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
#define TLB_256MB_SIZE 0x10000000
#define TLB_16MB_SIZE 0x01000000
#define TLB_1MB_SIZE 0x00100000
#define TLB_256KB_SIZE 0x00040000
#define TLB_64KB_SIZE 0x00010000
#define TLB_16KB_SIZE 0x00004000
#define TLB_4KB_SIZE 0x00001000
#define TLB_1KB_SIZE 0x00000400
#define TLB_WORD0_EPN_MASK 0xFFFFFC00
#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD0_V_MASK 0x00000200
#define TLB_WORD0_V_ENABLE 0x00000200
#define TLB_WORD0_V_DISABLE 0x00000000
#define TLB_WORD0_TS_MASK 0x00000100
#define TLB_WORD0_TS_1 0x00000100
#define TLB_WORD0_TS_0 0x00000000
#define TLB_WORD0_SIZE_MASK 0x000000F0
#define TLB_WORD0_SIZE_1KB 0x00000000
#define TLB_WORD0_SIZE_4KB 0x00000010
#define TLB_WORD0_SIZE_16KB 0x00000020
#define TLB_WORD0_SIZE_64KB 0x00000030
#define TLB_WORD0_SIZE_256KB 0x00000040
#define TLB_WORD0_SIZE_1MB 0x00000050
#define TLB_WORD0_SIZE_16MB 0x00000070
#define TLB_WORD0_SIZE_256MB 0x00000090
#define TLB_WORD0_TPAR_MASK 0x0000000F
#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD1_RPN_MASK 0xFFFFFC00
#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
#define TLB_WORD1_PAR1_MASK 0x00000300
#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
#define TLB_WORD1_PAR1_0 0x00000000
#define TLB_WORD1_PAR1_1 0x00000100
#define TLB_WORD1_PAR1_2 0x00000200
#define TLB_WORD1_PAR1_3 0x00000300
#define TLB_WORD1_ERPN_MASK 0x0000000F
#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
#define TLB_WORD2_PAR2_MASK 0xC0000000
#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
#define TLB_WORD2_PAR2_0 0x00000000
#define TLB_WORD2_PAR2_1 0x40000000
#define TLB_WORD2_PAR2_2 0x80000000
#define TLB_WORD2_PAR2_3 0xC0000000
#define TLB_WORD2_U0_MASK 0x00008000
#define TLB_WORD2_U0_ENABLE 0x00008000
#define TLB_WORD2_U0_DISABLE 0x00000000
#define TLB_WORD2_U1_MASK 0x00004000
#define TLB_WORD2_U1_ENABLE 0x00004000
#define TLB_WORD2_U1_DISABLE 0x00000000
#define TLB_WORD2_U2_MASK 0x00002000
#define TLB_WORD2_U2_ENABLE 0x00002000
#define TLB_WORD2_U2_DISABLE 0x00000000
#define TLB_WORD2_U3_MASK 0x00001000
#define TLB_WORD2_U3_ENABLE 0x00001000
#define TLB_WORD2_U3_DISABLE 0x00000000
#define TLB_WORD2_W_MASK 0x00000800
#define TLB_WORD2_W_ENABLE 0x00000800
#define TLB_WORD2_W_DISABLE 0x00000000
#define TLB_WORD2_I_MASK 0x00000400
#define TLB_WORD2_I_ENABLE 0x00000400
#define TLB_WORD2_I_DISABLE 0x00000000
#define TLB_WORD2_M_MASK 0x00000200
#define TLB_WORD2_M_ENABLE 0x00000200
#define TLB_WORD2_M_DISABLE 0x00000000
#define TLB_WORD2_G_MASK 0x00000100
#define TLB_WORD2_G_ENABLE 0x00000100
#define TLB_WORD2_G_DISABLE 0x00000000
#define TLB_WORD2_E_MASK 0x00000080
#define TLB_WORD2_E_ENABLE 0x00000080
#define TLB_WORD2_E_DISABLE 0x00000000
#define TLB_WORD2_UX_MASK 0x00000020
#define TLB_WORD2_UX_ENABLE 0x00000020
#define TLB_WORD2_UX_DISABLE 0x00000000
#define TLB_WORD2_UW_MASK 0x00000010
#define TLB_WORD2_UW_ENABLE 0x00000010
#define TLB_WORD2_UW_DISABLE 0x00000000
#define TLB_WORD2_UR_MASK 0x00000008
#define TLB_WORD2_UR_ENABLE 0x00000008
#define TLB_WORD2_UR_DISABLE 0x00000000
#define TLB_WORD2_SX_MASK 0x00000004
#define TLB_WORD2_SX_ENABLE 0x00000004
#define TLB_WORD2_SX_DISABLE 0x00000000
#define TLB_WORD2_SW_MASK 0x00000002
#define TLB_WORD2_SW_ENABLE 0x00000002
#define TLB_WORD2_SW_DISABLE 0x00000000
#define TLB_WORD2_SR_MASK 0x00000001
#define TLB_WORD2_SR_ENABLE 0x00000001
#define TLB_WORD2_SR_DISABLE 0x00000000
/*----------------------------------------------------------------------------+
| Board specific defines.
+----------------------------------------------------------------------------*/
#define NONCACHE_MEMORY_SIZE (64*1024)
#define NONCACHE_AREA0_ENDOFFSET (64*1024)
#define NONCACHE_AREA1_ENDOFFSET (32*1024)
#define FLASH_SECTORSIZE 0x00010000
/* SDRAM MICRON */
#define SDRAM_MICRON 0x2C
#define SDRAM_TRUE 1
#define SDRAM_FALSE 0
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXBANKSPERDIMM 2
#define MAXRANKSPERDIMM 2
#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
#define ERROR_STR_LENGTH 256
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
/*----------------------------------------------------------------------------+
| SDR Configuration registers
+----------------------------------------------------------------------------*/
/* Serial Device Strap Reg 0 */
#define sdr_pstrp0 0x0040
#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
/* Serial Device Enabled - Addr = 0xA8 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
/* Serial Device Enabled - Addr = 0xA4 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
/* Pin Straps Reg */
#define SDR0_PSTRP0 0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
/* fpgareg - defines are in include/config/YUCCA.h */
#define SDR0_CUST0_ENET3_MASK 0x00000080
#define SDR0_CUST0_ENET3_COPPER 0x00000000
#define SDR0_CUST0_ENET3_FIBER 0x00000080
#define SDR0_CUST0_RGMII3_MASK 0x00000070
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
#define SDR0_CUST0_RGMII3_DISAB 0x00000000
#define SDR0_CUST0_RGMII3_RTBI 0x00000040
#define SDR0_CUST0_RGMII3_RGMII 0x00000050
#define SDR0_CUST0_RGMII3_TBI 0x00000060
#define SDR0_CUST0_RGMII3_GMII 0x00000070
#define SDR0_CUST0_ENET2_MASK 0x00000008
#define SDR0_CUST0_ENET2_COPPER 0x00000000
#define SDR0_CUST0_ENET2_FIBER 0x00000008
#define SDR0_CUST0_RGMII2_MASK 0x00000007
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
#define SDR0_CUST0_RGMII2_DISAB 0x00000000
#define SDR0_CUST0_RGMII2_RTBI 0x00000004
#define SDR0_CUST0_RGMII2_RGMII 0x00000005
#define SDR0_CUST0_RGMII2_TBI 0x00000006
#define SDR0_CUST0_RGMII2_GMII 0x00000007
#define ONE_MILLION 1000000
#define ONE_BILLION 1000000000
/*----------------------------------------------------------------------------+
| X
| XX
| XX XXX XXXXX XX XXX XXXXX
| XX XX X XXX XX XX
| XX XX XXXXXX XX XX
| XX XX X XX XX XX XX
| XXX XX XXXXX X XXXX XXX
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Declare Configuration values
+----------------------------------------------------------------------------*/
typedef enum config_selection {
CONFIG_NOT_SELECTED,
CONFIG_SELECTED
} config_selection_t;
typedef enum config_list {
UART2_IN_SERVICE_MODE,
CPU_TRACE_MODE,
UART1_CTS_RTS,
CONFIG_NB
} config_list_t;
#define MAX_CONFIG_SELECT_NB 3
#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
#define BOARD_INFO_CPU_TRACE_MODE 2
#define BOARD_INFO_UART1_CTS_RTS_MODE 4
void force_bup_config_selection(config_selection_t *confgi_select_P);
void update_config_selection_table(config_selection_t *config_select_P);
void display_config_selection(config_selection_t *config_select_P);
/*----------------------------------------------------------------------------+
| XX
|
| XXXX XX XXX XXX XXXX
| XX XX XX XX XX XX
| XX XXX XX XX XX XX XX
| XX XX XXXXX XX XX XX
| XXXX XX XXXX XXXX
| XXXX
|
|
|
| +------------------------------------------------------------------+
| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
| +----------------------+------------------+-----+------------+-----+
| | | | | | |
| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
| | GPIO0_8 | PERREADY | I | TRCES4 | NA |
| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
| | GPIO0_16 | IRQ5 | I | UART2RX | I |
| | GPIO0_17 | PERBE0_N | O | UART2TX | O |
| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
| | GPIO0_30 | UART1RX | I | NA | NA |
| | GPIO0_31 | UART1TX | O | NA | NA |
| | | | | | |
| +----------------------+------------------+-----+------------+-----+
|
+----------------------------------------------------------------------------*/
unsigned long auto_calc_speed(void);
/*----------------------------------------------------------------------------+
| Prototypes
+----------------------------------------------------------------------------*/
void print_evb440spe_info(void);
int onboard_pci_arbiter_selected(int core_pci);
#ifdef __cplusplus
}
#endif
#endif /* __YUCCA_H_ */

5
common/cmd_bdinfo.c
View File

@ -61,11 +61,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440SP)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */

6
common/serial.c
View File

@ -42,7 +42,11 @@ struct serial_device *default_serial_console (void)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
return &serial0_device;
#if defined(CONFIG_UART1_CONSOLE)
return &serial1_device;
#else
return &serial0_device;
#endif
#else
#error No default console
#endif

9
cpu/ppc4xx/405gp_pci.c
View File

@ -438,7 +438,7 @@ void pci_440_init (struct pci_controller *hose)
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long strap;
mfsdr(sdr_sdstp1,strap);
@ -502,7 +502,7 @@ void pci_440_init (struct pci_controller *hose)
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#elif defined(PCIX0_BRDGOPT1)
@ -520,8 +520,13 @@ void pci_440_init (struct pci_controller *hose)
out32r( PCIX0_POM0SA, 0 ); /* disable */
out32r( PCIX0_POM1SA, 0 ); /* disable */
out32r( PCIX0_POM2SA, 0 ); /* disable */
#if defined(CONFIG_440SPE)
out32r( PCIX0_POM0LAL, 0x10000000 );
out32r( PCIX0_POM0LAH, 0x0000000c );
#else
out32r( PCIX0_POM0LAL, 0x00000000 );
out32r( PCIX0_POM0LAH, 0x00000003 );
#endif
out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */

78
cpu/ppc4xx/4xx_enet.c
View File

@ -181,6 +181,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
#if defined(CONFIG_440SPE)
unsigned long mfr;
#endif
out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
@ -202,8 +205,23 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
}
/* EMAC RESET */
#if defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= 0x08000000;
mtsdr(sdr_mfr, mfr);
#endif
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
#if defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~0x08000000;
mtsdr(sdr_mfr, mfr);
#endif
#ifndef CONFIG_NETCONSOLE
hw_p->print_speed = 1; /* print speed message again next time */
#endif
@ -301,7 +319,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
return ((int)pfc1);
}
#endif
#endif /* CONFIG_440_GX */
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
@ -314,12 +332,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
sys_info_t sysinfo;
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
int ethgroup = -1;
#endif
#endif
#if defined(CONFIG_440SPE)
unsigned long mfr;
#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
@ -330,7 +352,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
return -1;
}
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
@ -360,6 +382,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->stats.pkts_tx = 0;
hw_p->stats.pkts_rx = 0;
hw_p->stats.pkts_handled = 0;
hw_p->print_speed = 1; /* print speed message again next time */
#endif
hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
@ -373,7 +396,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
#if defined(CONFIG_440) && !defined(CONFIG_440SP)
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
/* set RMII mode */
/* NOTE: 440GX spec states that mode is mutually exclusive */
/* NOTE: Therefore, disable all other EMACS, since we handle */
@ -406,6 +429,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
#if defined(CONFIG_440SPE)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= 0x08000000;
mtsdr(sdr_mfr, mfr);
#endif
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
__asm__ volatile ("eieio");
@ -416,7 +445,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440SPE)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~0x08000000;
mtsdr(sdr_mfr, mfr);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@ -468,7 +504,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->first_init == 0) {
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
@ -544,7 +580,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
#if defined(CONFIG_440) && !defined(CONFIG_440SP)
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
@ -575,7 +611,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@ -759,8 +795,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set speed */
if (speed == _1000BASET) {
#if defined(CONFIG_440SP)
#define SDR0_PFC1_EM_1000 0x00200000
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
pfc1 |= SDR0_PFC1_EM_1000;
@ -787,7 +822,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440GP has a 64 byte burst length */
/* 440s has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else
/* 405s have a 16 byte burst length */
@ -895,7 +930,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
#if defined (CONFIG_440)
#if defined(CONFIG_440SP)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*
* Hack: On 440SP all enet irq sources are located on UIC1
* Needs some cleanup. --sr
@ -1367,20 +1402,19 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#endif
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
bis->bi_phymode[0] = 0;
#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
bis->bi_phymode[1] = 0;
#endif
#if defined(CONFIG_440GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
bis->bi_phymode[1] = 0;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
#if defined (CONFIG_440GX)
ppc_4xx_eth_setup_bridge(0, bis);
#endif
#endif
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
@ -1478,9 +1512,15 @@ int ppc_4xx_eth_initialize (bd_t * bis)
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
#if defined(CONFIG_440SPE)
mal_ier =
MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
#else
mal_ier =
MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
MAL_IER_OPBE | MAL_IER_PLBE;
#endif
mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
@ -1510,11 +1550,13 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#else
emac0_dev = dev;
#endif
#if defined(CONFIG_NET_MULTI)
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
#endif
} /* end for each supported device */
return (1);
}

18
cpu/ppc4xx/cpu.c
View File

@ -82,7 +82,9 @@ int pci_arbiter_enabled(void)
return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
unsigned long val;
mfsdr(sdr_sdstp1, val);
@ -91,8 +93,8 @@ int pci_arbiter_enabled(void)
}
#endif
#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define I2C_BOOTROM
@ -102,7 +104,9 @@ int i2c_bootrom_enabled(void)
return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
unsigned long val;
mfsdr(sdr_sdcs, val);
@ -248,6 +252,12 @@ int checkcpu (void)
puts("SP Rev. B");
break;
case PVR_440SPe_RA:
puts("SPe 3GA533C");
break;
case PVR_440SPe_RB:
puts("SPe 3GB533C");
break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;

123
cpu/ppc4xx/interrupts.c
View File

@ -50,18 +50,22 @@ struct irq_action {
};
static struct irq_action irq_vecs[32];
void uic0_interrupt( void * parms); /* UIC0 handler */
#if defined(CONFIG_440)
static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
#endif /* CONFIG_440GX */
#endif /* CONFIG_440GX CONFIG_440SPE */
#if defined(CONFIG_440SPE)
static struct irq_action irq_vecs3[32]; /* For UIC3 */
void uic3_interrupt( void * parms); /* UIC3 handler */
#endif /* CONFIG_440SPE */
#endif /* CONFIG_440 */
@ -115,11 +119,16 @@ int interrupt_init_cpu (unsigned *decrementer_count)
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
#endif /* CONFIG_440GX */
#if defined(CONFIG_440SPE)
irq_vecs3[vec].handler = NULL;
irq_vecs3[vec].arg = NULL;
irq_vecs3[vec].count = 0;
#endif /* CONFIG_440SPE */
#endif
}
@ -221,6 +230,34 @@ void external_interrupt(struct pt_regs *regs)
} /* external_interrupt CONFIG_440GX */
#elif defined(CONFIG_440SPE)
void external_interrupt(struct pt_regs *regs)
{
ulong uic_msr;
/*
* Read masked interrupt status register to determine interrupt source
*/
/* 440 SPe uses base uic register */
uic_msr = mfdcr(uic0msr);
if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
uic1_interrupt(0);
if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
uic2_interrupt(0);
if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
uic3_interrupt(0);
if (uic_msr & ~(UICB0_ALL))
uic0_interrupt(0);
mtdcr(uic0sr, uic_msr);
return;
} /* external_interrupt CONFIG_440SPE */
#else
void external_interrupt(struct pt_regs *regs)
@ -266,7 +303,7 @@ void external_interrupt(struct pt_regs *regs)
}
#endif
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
@ -357,8 +394,8 @@ void uic1_interrupt( void * parms)
}
#endif /* defined(CONFIG_440) */
#if defined(CONFIG_440GX)
/* Handler for UIC1 interrupt */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
/* Handler for UIC2 interrupt */
void uic2_interrupt( void * parms)
{
ulong uic2_msr;
@ -384,7 +421,7 @@ void uic2_interrupt( void * parms)
(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
} else {
mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec);
}
/*
@ -402,6 +439,51 @@ void uic2_interrupt( void * parms)
}
#endif /* defined(CONFIG_440GX) */
#if defined(CONFIG_440SPE)
/* Handler for UIC3 interrupt */
void uic3_interrupt( void * parms)
{
ulong uic3_msr;
ulong msr_shift;
int vec;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic3_msr = mfdcr(uic3msr);
msr_shift = uic3_msr;
vec = 0;
while (msr_shift != 0) {
if (msr_shift & 0x80000000) {
/*
* Increment irq counter (for debug purpose only)
*/
irq_vecs3[vec].count++;
if (irq_vecs3[vec].handler != NULL) {
/* call isr */
(*irq_vecs3[vec].handler)(irq_vecs3[vec].arg);
} else {
mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec));
printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec);
}
/*
* After servicing the interrupt, we have to remove the status indicator.
*/
mtdcr(uic3sr, (0x80000000 >> vec));
}
/*
* Shift msr to next position and increment vector
*/
msr_shift <<= 1;
vec++;
}
}
#endif /* defined(CONFIG_440SPE) */
/****************************************************************************/
/*
@ -414,7 +496,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
@ -441,7 +523,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
irqa[i].arg = arg;
#if defined(CONFIG_440)
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
@ -464,7 +546,7 @@ void irq_free_handler (int vec)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
@ -485,7 +567,7 @@ void irq_free_handler (int vec)
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
@ -553,7 +635,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("\n");
#endif
#if defined(CONFIG_440GX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");
@ -566,6 +648,19 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("\n");
#endif
#if defined(CONFIG_440SPE)
printf ("\nUIC 3\n");
printf ("Nr Routine Arg Count\n");
for (vec=0; vec<32; vec++) {
if (irq_vecs3[vec].handler != NULL)
printf ("%02d %08lx %08lx %d\n",
vec+63, (ulong)irq_vecs3[vec].handler,
(ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count);
}
printf("\n");
#endif
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */

59
cpu/ppc4xx/miiphy.c
View File

@ -50,7 +50,7 @@
#include <405_mal.h>
#include <miiphy.h>
#undef ET_DEBUG
/***********************************************************/
/* Dump out to the screen PHY regs */
/***********************************************************/
@ -90,6 +90,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
PHY_ANLPAR_10);
miiphy_write (devname, addr, PHY_ANAR, adv);
miiphy_read (devname, addr, PHY_1000BTCR, &adv);
adv |= (0x0300);
miiphy_write (devname, addr, PHY_1000BTCR, adv);
/* Start/Restart aneg */
miiphy_read (devname, addr, PHY_BMCR, &ctl);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
@ -104,7 +108,7 @@ int phy_setup_aneg (char *devname, unsigned char addr)
/***********************************************************/
unsigned int miiphy_getemac_offset (void)
{
#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
unsigned long zmii;
unsigned long eoffset;
@ -155,10 +159,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
i = 0;
/* see if it is ready for sec */
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7);
if (i > 5) {
#if 0
#ifdef ET_DEBUG
sta_reg = in32 (EMAC_STACR + emac_reg);
printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
printf ("read err 1\n");
#endif
return -1;
@ -167,31 +173,41 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
#else
sta_reg |= EMAC_STACR_READ;
#endif
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
out32 (EMAC_STACR + emac_reg, sta_reg);
#if 0 /* test-only */
#ifdef ET_DEBUG
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
i = 0;
while ((sta_reg & EMAC_STACR_OC) == 0) {
while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7);
if (i > 5) {
return -1;
}
i++;
sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
}
if ((sta_reg & EMAC_STACR_PHYE) != 0) {
return -1;
@ -219,7 +235,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
/* see if it is ready for 1000 nsec */
i = 0;
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
if (i > 5)
return -1;
udelay (7);
@ -228,16 +244,21 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
#else
sta_reg |= EMAC_STACR_WRITE;
#endif
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
memcpy (&sta_reg, &value, 2); /* put in data */
out32 (EMAC_STACR + emac_reg, sta_reg);
@ -245,12 +266,18 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
/* wait for completion */
i = 0;
sta_reg = in32 (EMAC_STACR + emac_reg);
while ((sta_reg & EMAC_STACR_OC) == 0) {
#ifdef ET_DEBUG
printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7);
if (i > 5)
return -1;
i++;
sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
}
if ((sta_reg & EMAC_STACR_PHYE) != 0)

39
cpu/ppc4xx/serial.c
View File

@ -275,11 +275,11 @@ int serial_tstc ()
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
#if defined(CONFIG_440SP)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -309,14 +309,18 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440GX */
@ -437,7 +441,8 @@ int serial_init(void)
unsigned long tmp;
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
@ -466,7 +471,9 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
@ -607,8 +614,28 @@ void serial_setbrg (void)
#else
udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
#endif /* CONFIG_405EP */
#if !defined(CFG_EXT_SERIAL_CLOCK) && \
( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE) )
serial_divs (gd->baudrate, &udiv, &bdiv);
tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mtsdr (UART0_SDR, tmp);
} else {
mtsdr (UART1_SDR, tmp);
}
#else
mtsdr (UART0_SDR, tmp);
#endif
#else
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
#if defined(CONFIG_SERIAL_MULTI)
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */

254
cpu/ppc4xx/speed.c
View File

@ -29,7 +29,11 @@
DECLARE_GLOBAL_DATA_PTR;
#define ONE_BILLION 1000000000
#ifdef DEBUG
#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
@ -283,7 +287,7 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
@ -326,6 +330,26 @@ void get_sys_info (sys_info_t * sysInfo)
unsigned long m;
unsigned long prbdv0;
#if defined(CONFIG_440SPE)
unsigned long sys_freq;
unsigned long sys_per=0;
unsigned long msr;
unsigned long pci_clock_per;
unsigned long sdr_ddrpll;
/*-------------------------------------------------------------------------+
| Get the system clock period.
+-------------------------------------------------------------------------*/
sys_per = determine_sysper();
msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */
/*-------------------------------------------------------------------------+
| Calculate the system clock speed from the period.
+-------------------------------------------------------------------------*/
sys_freq=(ONE_BILLION/sys_per)*1000;
#endif
/* Extract configured divisors */
mfsdr( sdr_sdstp0,strp0 );
mfsdr( sdr_sdstp1,strp1 );
@ -360,12 +384,238 @@ void get_sys_info (sys_info_t * sysInfo)
m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
/* Now calculate the individual clocks */
#if defined(CONFIG_440SPE)
sysInfo->freqVCOMhz = (m * sys_freq) ;
#else
sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
#endif
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
#if defined(CONFIG_440SPE)
/* Determine PCI Clock Period */
pci_clock_per = determine_pci_clock_per();
sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
mfsdr(sdr_ddr0, sdr_ddrpll);
sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
#endif
}
#endif
#if defined(CONFIG_440SPE)
unsigned long determine_sysper(void)
{
unsigned int fpga_clocking_reg;
unsigned int master_clock_selection;
unsigned long master_clock_per = 0;
unsigned long fb_div_selection;
unsigned int vco_div_reg_value;
unsigned long vco_div_selection;
unsigned long sys_per = 0;
int extClkVal;
/*-------------------------------------------------------------------------+
| Read FPGA reg 0 and reg 1 to get FPGA reg information
+-------------------------------------------------------------------------*/
fpga_clocking_reg = in16(FPGA_REG16);
/* Determine Master Clock Source Selection */
master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
switch(master_clock_selection) {
case FPGA_REG16_MASTER_CLK_66_66:
master_clock_per = PERIOD_66_66MHZ;
break;
case FPGA_REG16_MASTER_CLK_50:
master_clock_per = PERIOD_50_00MHZ;
break;
case FPGA_REG16_MASTER_CLK_33_33:
master_clock_per = PERIOD_33_33MHZ;
break;
case FPGA_REG16_MASTER_CLK_25:
master_clock_per = PERIOD_25_00MHZ;
break;
case FPGA_REG16_MASTER_CLK_EXT:
if ((extClkVal==EXTCLK_33_33)
&& (extClkVal==EXTCLK_50)
&& (extClkVal==EXTCLK_66_66)
&& (extClkVal==EXTCLK_83)) {
/* calculate master clock period from external clock value */
master_clock_per=(ONE_BILLION/extClkVal) * 1000;
} else {
/* Unsupported */
DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
hang();
}
break;
default:
/* Unsupported */
DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
hang();
break;
}
/* Determine FB divisors values */
if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
fb_div_selection = FPGA_FB_DIV_6;
else
fb_div_selection = FPGA_FB_DIV_12;
} else {
if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
fb_div_selection = FPGA_FB_DIV_10;
else
fb_div_selection = FPGA_FB_DIV_20;
}
/* Determine VCO divisors values */
vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
switch(vco_div_reg_value) {
case FPGA_REG16_VCO_DIV_4:
vco_div_selection = FPGA_VCO_DIV_4;
break;
case FPGA_REG16_VCO_DIV_6:
vco_div_selection = FPGA_VCO_DIV_6;
break;
case FPGA_REG16_VCO_DIV_8:
vco_div_selection = FPGA_VCO_DIV_8;
break;
case FPGA_REG16_VCO_DIV_10:
default:
vco_div_selection = FPGA_VCO_DIV_10;
break;
}
if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
switch(master_clock_per) {
case PERIOD_25_00MHZ:
if (fb_div_selection == FPGA_FB_DIV_12) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_75_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_50_00MHZ;
}
break;
case PERIOD_33_33MHZ:
if (fb_div_selection == FPGA_FB_DIV_6) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_50_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_33_33MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_10) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_83_33MHZ;
if (vco_div_selection == FPGA_VCO_DIV_10)
sys_per = PERIOD_33_33MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_12) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_100_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_66_66MHZ;
if (vco_div_selection == FPGA_VCO_DIV_8)
sys_per = PERIOD_50_00MHZ;
}
break;
case PERIOD_50_00MHZ:
if (fb_div_selection == FPGA_FB_DIV_6) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_75_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_50_00MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_10) {
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_83_33MHZ;
if (vco_div_selection == FPGA_VCO_DIV_10)
sys_per = PERIOD_50_00MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_12) {
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_100_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_8)
sys_per = PERIOD_75_00MHZ;
}
break;
case PERIOD_66_66MHZ:
if (fb_div_selection == FPGA_FB_DIV_6) {
if (vco_div_selection == FPGA_VCO_DIV_4)
sys_per = PERIOD_100_00MHZ;
if (vco_div_selection == FPGA_VCO_DIV_6)
sys_per = PERIOD_66_66MHZ;
if (vco_div_selection == FPGA_VCO_DIV_8)
sys_per = PERIOD_50_00MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_10) {
if (vco_div_selection == FPGA_VCO_DIV_8)
sys_per = PERIOD_83_33MHZ;
if (vco_div_selection == FPGA_VCO_DIV_10)
sys_per = PERIOD_66_66MHZ;
}
if (fb_div_selection == FPGA_FB_DIV_12) {
if (vco_div_selection == FPGA_VCO_DIV_8)
sys_per = PERIOD_100_00MHZ;
}
break;
default:
break;
}
if (sys_per == 0) {
/* Other combinations are not supported */
DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
hang();
}
} else {
/* calcul system clock without cheking */
/* if engineering option clock no check is selected */
/* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
}
return(sys_per);
}
/*-------------------------------------------------------------------------+
| determine_pci_clock_per.
+-------------------------------------------------------------------------*/
unsigned long determine_pci_clock_per(void)
{
unsigned long pci_clock_selection, pci_period;
/*-------------------------------------------------------------------------+
| Read FPGA reg 6 to get PCI 0 FPGA reg information
+-------------------------------------------------------------------------*/
pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
switch (pci_clock_selection) {
case FPGA_REG16_PCI0_CLK_133_33:
pci_period = PERIOD_133_33MHZ;
break;
case FPGA_REG16_PCI0_CLK_100:
pci_period = PERIOD_100_00MHZ;
break;
case FPGA_REG16_PCI0_CLK_66_66:
pci_period = PERIOD_66_66MHZ;
break;
default:
pci_period = PERIOD_33_33MHZ;;
break;
}
return(pci_period);
}
#endif

70
cpu/ppc4xx/start.S
View File

@ -155,6 +155,11 @@
/**************************************************************************/
_start_440:
/*----------------------------------------------------------------+
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
addi r0,r0,0x0000
mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/
@ -166,7 +171,7 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
@ -200,6 +205,33 @@ _start_440:
ori r1,r1,0x6000 /* cache touch */
mtspr ccr0,r1
#if defined (CONFIG_440SPE)
/*----------------------------------------------------------------+
| Initialize Core Configuration Reg1.
| a. ICDPEI: Record even parity. Normal operation.
| b. ICTPEI: Record even parity. Normal operation.
| c. DCTPEI: Record even parity. Normal operation.
| d. DCDPEI: Record even parity. Normal operation.
| e. DCUPEI: Record even parity. Normal operation.
| f. DCMPEI: Record even parity. Normal operation.
| g. FCOM: Normal operation
| h. MMUPEI: Record even parity. Normal operation.
| i. FFF: Flush only as much data as necessary.
| j. TCS: Timebase increments from externally supplied clock
+-----------------------------------------------------------------*/
addis r0, r0, 0x0000
ori r0, r0, 0x0080
mtspr ccr1, r0
/*----------------------------------------------------------------+
| Reset the timebase.
| The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/
addi r0, r0, 0x0000
mtspr tbl, r0
mtspr tbu, r0
#endif
/*----------------------------------------------------------------*/
/* Setup interrupt vectors */
/*----------------------------------------------------------------*/
@ -261,15 +293,26 @@ _start_440:
mtspr ivlim,r1
mtspr dvlim,r1
/*----------------------------------------------------------------+
|Initialize MMUCR[STID] = 0.
+-----------------------------------------------------------------*/
mfspr r0,mmucr
addis r1,0,0xFFFF
ori r1,r1,0xFF00
and r0,r0,r1
mtspr mmucr,r0
/*----------------------------------------------------------------*/
/* Clear all TLB entries -- TID = 0, TS = 0 */
/*----------------------------------------------------------------*/
mtspr mmucr,r0
addis r0,0,0x0000
li r1,0x003f /* 64 TLB entries */
mtctr r1
0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
tlbwe r0,r1,0x0001
tlbwe r0,r1,0x0002
subi r1,r1,0x0001
bdnz 0b
bdnz rsttlb
/*----------------------------------------------------------------*/
/* TLB entry setup -- step thru tlbtab */
@ -377,7 +420,7 @@ _start:
addi r3,r3,32
bdnz ..d_ag
#else
#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
@ -404,6 +447,19 @@ _start:
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr isram0_sb3cr,r1
#elif defined(CONFIG_440SPE)
lis r1,0x0000 /* BAS = 0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x0001
ori r1,r1,0x0984 /* second 64k */
mtdcr isram0_sb1cr,r1
lis r1, 0x0002
ori r1,r1, 0x0984 /* third 64k */
mtdcr isram0_sb2cr,r1
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr isram0_sb3cr,r1
#else
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
@ -1197,7 +1253,7 @@ ppcSync:
*/
.globl relocate_code
relocate_code:
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
/*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled.
@ -1412,7 +1468,7 @@ trap_init:
cmplw 0, r7, r8
blt 4b
#if !defined(CONFIG_440_GX)
#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtmsr r7 /* change MSR */

43
cpu/ppc4xx/vecnum.h
View File

@ -31,7 +31,48 @@
#ifndef _VECNUMS_H_
#define _VECNUMS_H_
#if defined(CONFIG_440SP)
#if defined(CONFIG_440SPE)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_IIC0 2 /* IIC0 */
#define VECNUM_IIC1 3 /* IIC1 */
#define VECNUM_PIM 4 /* PCI inbound message */
#define VECNUM_PCRW 5 /* PCI command reg write */
#define VECNUM_PPM 6 /* PCI power management */
#define VECNUM_MSI0 7 /* PCI MSI level 0 */
#define VECNUM_MSI1 8 /* PCI MSI level 0 */
#define VECNUM_MSI2 9 /* PCI MSI level 0 */
#define VECNUM_D0 12 /* DMA channel 0 */
#define VECNUM_D1 13 /* DMA channel 1 */
#define VECNUM_D2 14 /* DMA channel 2 */
#define VECNUM_D3 15 /* DMA channel 3 */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */
#define VECNUM_MS (32 + 1 ) /* MAL SERR */
#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
/* UIC 2 */
#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */
#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */
#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */
#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */
#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */
#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */
#elif defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */

2
drivers/pci_indirect.c
View File

@ -60,7 +60,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \

10
include/405_mal.h
View File

@ -92,11 +92,21 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#ifdef CONFIG_440SPE
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
#define MAL_IER_DE 0x00000010
#define MAL_IER_OTE 0x00000004
#define MAL_IER_OE 0x00000002
#define MAL_IER_PE 0x00000001
#else
#define MAL_IER_DE 0x00000010
#define MAL_IER_NE 0x00000008
#define MAL_IER_TE 0x00000004
#define MAL_IER_OPBE 0x00000002
#define MAL_IER_PLBE 0x00000001
#endif
/* MAL Channel Active Set and Reset Registers */
#define MAL_TXRX_CASR (0x80000000)

41
include/asm-ppc/mmu.h
View File

@ -470,4 +470,45 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
#ifdef CONFIG_440SPE
/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define DCCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(454<<1)
#define ICCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(966<<1)
#define DCREAD(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
#define ICREAD(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(998<<1)
#define TLBSX(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define TLBWE(rs,ra,ws) .long 0x7c000000|\
(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
#define TLBRE(rt,ra,ws) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define MSYNC .long 0x7c000000|\
(598<<1)
#define MBAR_INST .long 0x7c000000|\
(854<<1)
/*----------------------------------------------------------------------------+
| Following instruction is not available in PPC405 mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define TLBRE(rt,ra,ws) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
#endif
#endif /* _PPC_MMU_H_ */

2
include/asm-ppc/processor.h
View File

@ -735,6 +735,8 @@
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
#define PVR_440SPe_RA 0x53421890
#define PVR_440SPe_RB 0x53521891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000

1948
include/bmp_logo.h
View File

File diff suppressed because it is too large Load Diff

4
include/common.h
View File

@ -458,6 +458,10 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif

518
include/configs/yucca.h Normal file
View File

@ -0,0 +1,518 @@
/*
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* 1 january 2005 Alain Saurel <asaurel@amcc.com>
* Adapted to current Das U-Boot source
***********************************************************************/
/************************************************************************
* yucca.h - configuration for AMCC 440SPe Ref (yucca)
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
#define CONFIG_IDENT_STRING "\nU_440SPe_V1R01 level06"
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define EXTCLK_33_33 33333333
#define EXTCLK_66_66 66666666
#define EXTCLK_50 50000000
#define EXTCLK_83 83333333
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
#undef ENABLE_ECC
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
#define CFG_FPGA_BASE 0xe2000000 /* epld */
#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK
/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */
#define IIC0_DIMM0_ADDR 0x53
#define IIC0_DIMM1_ADDR 0x52
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
/* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* #endif */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=/dev/nfs rw"
#define CONFIG_BOOTCOMMAND "bootm E7C00000" /* autoboot command */
#define CONFIG_BOOTDELAY -1 /* -1 to disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#undef CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 192.168.80.10
#define CONFIG_ETHADDR 00:04:AC:01:CA:FE
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_EXTRA_ENV_SETTINGS \
"loads_echo=1\0" \
"netdev=eth0\0" \
"hostname=yucca\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk-4.0/ppc_4xx\0" \
"bootfile=yucca/uImage\0" \
"kernel_addr=E7F10000\0" \
"ramdisk_addr=E7F20000\0" \
"load=tftp 100000 yuca/u-boot.bin\0" \
"update=protect off 2:4-7;era 2:4-7;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_DHCP | \
CFG_CMD_PING | \
CFG_CMD_DIAG | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR 0xfffa0000
/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW i /* show pci devices on startup */
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
/*
* NETWORK Support (PCI):
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* FB Divisor selection */
#define FPGA_FB_DIV_6 6
#define FPGA_FB_DIV_10 10
#define FPGA_FB_DIV_12 12
#define FPGA_FB_DIV_20 20
/* VCO Divisor selection */
#define FPGA_VCO_DIV_4 4
#define FPGA_VCO_DIV_6 6
#define FPGA_VCO_DIV_8 8
#define FPGA_VCO_DIV_10 10
/*----------------------------------------------------------------------------+
| FPGA registers and bit definitions
+----------------------------------------------------------------------------*/
/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
/* TLB initialization makes it correspond to logical address 0xE2000000. */
/* => Done init_chip.s in bootlib */
#define FPGA_REG_BASE_ADDR 0xE2000000
#define FPGA_GPIO_BASE_ADDR 0xE2010000
#define FPGA_INT_BASE_ADDR 0xE2020000
/*----------------------------------------------------------------------------+
| Display
+----------------------------------------------------------------------------*/
#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
/*----------------------------------------------------------------------------+
| ethernet/reset/boot Register 1
+----------------------------------------------------------------------------*/
#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
#define FPGA_REG10_10MHZ_ENABLE 0x8000
#define FPGA_REG10_100MHZ_ENABLE 0x4000
#define FPGA_REG10_GIGABIT_ENABLE 0x2000
#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
#define FPGA_REG10_RESET_ETH 0x0800
#define FPGA_REG10_AUTO_NEG_DIS 0x0400
#define FPGA_REG10_INTP_ETH 0x0200
#define FPGA_REG10_RESET_HISR 0x0080
#define FPGA_REG10_ENABLE_DISPLAY 0x0040
#define FPGA_REG10_RESET_SDRAM 0x0020
#define FPGA_REG10_OPER_BOOT 0x0010
#define FPGA_REG10_SRAM_BOOT 0x0008
#define FPGA_REG10_SMALL_BOOT 0x0004
#define FPGA_REG10_FORCE_COLA 0x0002
#define FPGA_REG10_COLA_MANUAL 0x0001
#define FPGA_REG10_SDRAM_ENABLE 0x0020
#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
/*----------------------------------------------------------------------------+
| MUX control
+----------------------------------------------------------------------------*/
#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
#define FPGA_REG12_EBC_CTL 0x8000
#define FPGA_REG12_UART1_CTS_RTS 0x4000
#define FPGA_REG12_UART0_RX_ENABLE 0x2000
#define FPGA_REG12_UART1_RX_ENABLE 0x1000
#define FPGA_REG12_UART2_RX_ENABLE 0x0800
#define FPGA_REG12_EBC_OUT_ENABLE 0x0400
#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
#define FPGA_REG12_GPIO_SELECT 0x0010
#define FPGA_REG12_GPIO_CHREG 0x0008
#define FPGA_REG12_GPIO_CLK_CHREG 0x0004
#define FPGA_REG12_GPIO_OETRI 0x0002
#define FPGA_REG12_EBC_ERROR 0x0001
/*----------------------------------------------------------------------------+
| PCI Clock control
+----------------------------------------------------------------------------*/
#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
#define FPGA_REG16_PCI_CLK_CTL0 0x8000
#define FPGA_REG16_PCI_CLK_CTL1 0x4000
#define FPGA_REG16_PCI_CLK_CTL2 0x2000
#define FPGA_REG16_PCI_CLK_CTL3 0x1000
#define FPGA_REG16_PCI_CLK_CTL4 0x0800
#define FPGA_REG16_PCI_CLK_CTL5 0x0400
#define FPGA_REG16_PCI_CLK_CTL6 0x0200
#define FPGA_REG16_PCI_CLK_CTL7 0x0100
#define FPGA_REG16_PCI_CLK_CTL8 0x0080
#define FPGA_REG16_PCI_CLK_CTL9 0x0040
#define FPGA_REG16_PCI_EXT_ARB0 0x0020
#define FPGA_REG16_PCI_MODE_1 0x0010
#define FPGA_REG16_PCI_TARGET_MODE 0x0008
#define FPGA_REG16_PCI_INTP_MODE 0x0004
/* FB1 Divisor selection */
#define FPGA_REG16_FB2_DIV_MASK 0x1000
#define FPGA_REG16_FB2_DIV_LOW 0x0000
#define FPGA_REG16_FB2_DIV_HIGH 0x1000
/* FB2 Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_FB1_DIV_MASK 0x2000
#define FPGA_REG16_FB1_DIV_LOW 0x0000
#define FPGA_REG16_FB1_DIV_HIGH 0x2000
/* PCI0 Clock Selection */
/* S3 switch on Board */
#define FPGA_REG16_PCI0_CLK_MASK 0x0c00
#define FPGA_REG16_PCI0_CLK_33_33 0x0000
#define FPGA_REG16_PCI0_CLK_66_66 0x0800
#define FPGA_REG16_PCI0_CLK_100 0x0400
#define FPGA_REG16_PCI0_CLK_133_33 0x0c00
/* VCO Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_VCO_DIV_MASK 0xc000
#define FPGA_REG16_VCO_DIV_4 0x0000
#define FPGA_REG16_VCO_DIV_8 0x4000
#define FPGA_REG16_VCO_DIV_6 0x8000
#define FPGA_REG16_VCO_DIV_10 0xc000
/* Master Clock Selection */
/* S3, S4 switches on Board */
#define FPGA_REG16_MASTER_CLK_MASK 0x01c0
#define FPGA_REG16_MASTER_CLK_EXT 0x0000
#define FPGA_REG16_MASTER_CLK_66_66 0x0040
#define FPGA_REG16_MASTER_CLK_50 0x0080
#define FPGA_REG16_MASTER_CLK_33_33 0x00c0
#define FPGA_REG16_MASTER_CLK_25 0x0100
/*----------------------------------------------------------------------------+
| PCI Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
#define FPGA_REG18_PCI_PRSNT1 0x8000
#define FPGA_REG18_PCI_PRSNT2 0x4000
#define FPGA_REG18_PCI_INTA 0x2000
#define FPGA_REG18_PCI_SLOT0_INTP 0x1000
#define FPGA_REG18_PCI_SLOT1_INTP 0x0800
#define FPGA_REG18_PCI_SLOT2_INTP 0x0400
#define FPGA_REG18_PCI_SLOT3_INTP 0x0200
#define FPGA_REG18_PCI_PCI0_VC 0x0100
#define FPGA_REG18_PCI_PCI0_VTH1 0x0080
#define FPGA_REG18_PCI_PCI0_VTH2 0x0040
#define FPGA_REG18_PCI_PCI0_VTH3 0x0020
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
#define FPGA_REG1A_PE0_GLED 0x8000
#define FPGA_REG1A_PE1_GLED 0x4000
#define FPGA_REG1A_PE2_GLED 0x2000
#define FPGA_REG1A_PE0_YLED 0x1000
#define FPGA_REG1A_PE1_YLED 0x0800
#define FPGA_REG1A_PE2_YLED 0x0400
#define FPGA_REG1A_PE0_PWRON 0x0200
#define FPGA_REG1A_PE1_PWRON 0x0100
#define FPGA_REG1A_PE2_PWRON 0x0080
#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
#define FPGA_REG1A_PE_SPREAD0 0x0008
#define FPGA_REG1A_PE_SPREAD1 0x0004
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
#define FPGA_REG1C_PE1_ENDPOINT 0x4000
#define FPGA_REG1C_PE2_ENDPOINT 0x2000
#define FPGA_REG1C_PE0_PRSNT 0x1000
#define FPGA_REG1C_PE1_PRSNT 0x0800
#define FPGA_REG1C_PE2_PRSNT 0x0400
#define FPGA_REG1C_PE0_WAKE 0x0080
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
#define FPGA_REG1C_PE1_PERST 0x0080
#define FPGA_REG1C_PE2_PERST 0x0040
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define PERIOD_133_33MHZ 7500 /* 7,5ns */
#define PERIOD_100_00MHZ 10000 /* 10ns */
#define PERIOD_83_33MHZ 12000 /* 12ns */
#define PERIOD_75_00MHZ 13333 /* 13,333ns */
#define PERIOD_66_66MHZ 15000 /* 15ns */
#define PERIOD_50_00MHZ 20000 /* 20ns */
#define PERIOD_33_33MHZ 30000 /* 30ns */
#define PERIOD_25_00MHZ 40000 /* 40ns */
/*---------------------------------------------------------------------------*/
#endif /* __CONFIG_H */

1296
include/ppc440.h
View File

File diff suppressed because it is too large Load Diff

26
include/ppc4xx_enet.h
View File

@ -133,12 +133,21 @@ typedef struct emac_4xx_hw_st {
#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
!defined(CONFIG_440SP)
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define EMAC_NUM_DEV 2
#else
#define EMAC_NUM_DEV 1
#endif
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
#define EMAC_STACR_OC_MASK (0x00008000)
#else
#define EMAC_STACR_OC_MASK (0x00000000)
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
@ -323,7 +332,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@ -424,8 +433,21 @@ typedef struct emac_4xx_hw_st {
/* STA CONTROL REG */
#define EMAC_STACR_OC (0x00008000)
#define EMAC_STACR_PHYE (0x00004000)
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
#define EMAC_STACR_INDIRECT_MODE (0x00002000)
#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
#define EMAC_STACR_READ (0x00001000) /* $BUC */
#define EMAC_STACR_OP_MASK (0x00001800)
#define EMAC_STACR_MDIO_ADDR (0x00000000)
#define EMAC_STACR_MDIO_WRITE (0x00000800)
#define EMAC_STACR_MDIO_READ (0x00001800)
#define EMAC_STACR_MDIO_READ_INC (0x00001000)
#else
#define EMAC_STACR_WRITE (0x00002000)
#define EMAC_STACR_READ (0x00001000)
#endif
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
#define EMAC_STACR_CLK_66MHZ (0x00000400)
#define EMAC_STACR_CLK_100MHZ (0x00000C00)

11
lib_ppc/board.c
View File

@ -610,6 +610,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
@ -619,14 +624,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
board_early_init_r ();
#endif
gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
monitor_flash_len = (ulong)&__init_end - dest_addr;
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
/*
* We have to relocate the command table manually
*/