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imx: imx6: Move gpr_init() function to soc.c

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Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Breno Lima 2017-08-24 10:00:16 -03:00 committed by Stefano Babic
parent 962c78b1df
commit 3aa4b703b4
19 changed files with 19 additions and 200 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -90,6 +90,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
} }
u32 imx6_src_get_boot_mode(void); u32 imx6_src_get_boot_mode(void);
void gpr_init(void);
#endif /* CONFIG_MX6 */ #endif /* CONFIG_MX6 */
u32 get_nr_cpus(void); u32 get_nr_cpus(void);

17
arch/arm/mach-imx/mx6/soc.c
View File

@ -681,6 +681,23 @@ void imx_setup_hdmi(void)
} }
#endif #endif
void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
#ifdef CONFIG_IMX_BOOTAUX #ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{ {

11
board/bachmann/ot1200/ot1200.c
View File

@ -169,17 +169,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
int board_early_init_f(void) int board_early_init_f(void)
{ {
ccgr_init(); ccgr_init();

11
board/barco/platinum/platinum.h
View File

@ -75,15 +75,4 @@ static inline void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static inline void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
#endif /* _PLATINUM_H_ */ #endif /* _PLATINUM_H_ */

11
board/congatec/cgtqmx6eval/cgtqmx6eval.c
View File

@ -955,17 +955,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* Define a minimal structure so that the part number can be read via SPL */ /* Define a minimal structure so that the part number can be read via SPL */
struct mfgdata { struct mfgdata {
unsigned char tsize; unsigned char tsize;

11
board/el/el6x/el6x.c
View File

@ -570,17 +570,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* /*
* This section requires the differentiation between iMX6 Sabre boards, but * This section requires the differentiation between iMX6 Sabre boards, but
* for now, it will configure only for the mx6q variant. * for now, it will configure only for the mx6q variant.

11
board/engicam/common/spl.c
View File

@ -332,17 +332,6 @@ static void ccgr_init(void)
#endif #endif
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
#ifdef CONFIG_MX6QDL #ifdef CONFIG_MX6QDL

17
board/freescale/mx6sabreauto/mx6sabreauto.c
View File

@ -798,23 +798,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
static int mx6q_dcd_table[] = { static int mx6q_dcd_table[] = {
0x020e0798, 0x000C0000, 0x020e0798, 0x000C0000,
0x020e0758, 0x00000000, 0x020e0758, 0x00000000,

17
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -747,23 +747,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
static int mx6q_dcd_table[] = { static int mx6q_dcd_table[] = {
0x020e0798, 0x000C0000, 0x020e0798, 0x000C0000,
0x020e0758, 0x00000000, 0x020e0758, 0x00000000,

11
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -583,17 +583,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* /*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main) * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM * - we have a stack and a place to store GD, both in SRAM

11
board/kosagi/novena/novena_spl.c
View File

@ -550,17 +550,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* /*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main) * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM * - we have a stack and a place to store GD, both in SRAM

11
board/liebherr/mccmon6/spl.c
View File

@ -260,17 +260,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
if (is_cpu_type(MXC_CPU_MX6SOLO)) { if (is_cpu_type(MXC_CPU_MX6SOLO)) {

12
board/phytec/pcm058/pcm058.c
View File

@ -487,18 +487,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
struct mx6_ddr_sysinfo sysinfo = { struct mx6_ddr_sysinfo sysinfo = {

11
board/phytec/pfla02/pfla02.c
View File

@ -550,17 +550,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr) static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)
{ {
struct mx6_ddr_sysinfo sysinfo = { struct mx6_ddr_sysinfo sysinfo = {

11
board/solidrun/mx6cuboxi/mx6cuboxi.c
View File

@ -581,17 +581,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(int width) static void spl_dram_init(int width)
{ {
struct mx6_ddr_sysinfo sysinfo = { struct mx6_ddr_sysinfo sysinfo = {

11
board/toradex/apalis_imx6/apalis_imx6.c
View File

@ -1160,17 +1160,6 @@ static void ccgr_init(void)
writel(0x000000FB, &ccm->ccosr); writel(0x000000FB, &ccm->ccosr);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void ddr_init(int *table, int size) static void ddr_init(int *table, int size)
{ {
int i; int i;

11
board/toradex/colibri_imx6/colibri_imx6.c
View File

@ -1037,17 +1037,6 @@ static void ccgr_init(void)
writel(0x000000FB, &ccm->ccosr); writel(0x000000FB, &ccm->ccosr);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void ddr_init(int *table, int size) static void ddr_init(int *table, int size)
{ {
int i; int i;

11
board/udoo/udoo_spl.c
View File

@ -211,17 +211,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000FF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
if (is_cpu_type(MXC_CPU_MX6DL)) { if (is_cpu_type(MXC_CPU_MX6DL)) {

11
board/wandboard/spl.c
View File

@ -266,17 +266,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
if (is_cpu_type(MXC_CPU_MX6SOLO)) { if (is_cpu_type(MXC_CPU_MX6SOLO)) {