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imx: imx6: Move gpr_init() function to soc.c

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Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
MX6Q and MX6QP processors move it to the soc.c file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Breno Lima
2017-08-24 10:00:16 -03:00
committed by Stefano Babic
parent 962c78b1df
commit 3aa4b703b4
19 changed files with 19 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/mach-imx/sys_proto.h
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@@ -90,6 +90,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
}
u32 imx6_src_get_boot_mode(void);
void gpr_init(void);
#endif /* CONFIG_MX6 */
u32 get_nr_cpus(void);

17
arch/arm/mach-imx/mx6/soc.c
View File

@@ -681,6 +681,23 @@ void imx_setup_hdmi(void)
}
#endif
void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x77177717, &iomux->gpr[6]);
writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{