arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y
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CONFIG_OF_EMBED=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -28,6 +28,7 @@ CONFIG_OF_EMBED=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -34,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -29,6 +29,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -30,6 +30,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -39,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -32,6 +32,7 @@ CONFIG_CMD_CACHE=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_NAND=y
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@ -32,6 +32,7 @@ CONFIG_CMD_CACHE=y
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CONFIG_OF_EMBED=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_DM_MMC=y
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@ -32,6 +32,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_MTD_NOR_FLASH=y
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@ -31,6 +31,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_SPI_FLASH=y
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@ -34,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -38,6 +38,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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@ -50,4 +50,11 @@ config FPGA_SPARTAN3
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help
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Enable Spartan3 FPGA driver for loading in BIT format.
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config FPGA_ZYNQPL
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bool "Enable Xilinx FPGA for Zynq"
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depends on ARCH_ZYNQ
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help
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Enable FPGA driver for loading bitstream in BIT and BIN format
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on Xilinx Zynq devices.
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endmenu
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@ -269,8 +269,6 @@
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* Enable the PL to be downloaded */
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#define CONFIG_FPGA_ZYNQPL
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/* FIT support */
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#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
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