imx: mx6ull: update clock settings and CCM register map
Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
b4714616a0
commit
3974b7f6e0
@ -97,7 +97,10 @@ void enable_enet_clk(unsigned char enable)
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{
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u32 mask, *addr;
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if (is_mx6ul()) {
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if (is_mx6ull()) {
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mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
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addr = &imx_ccm->CCGR0;
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} else if (is_mx6ul()) {
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mask = MXC_CCM_CCGR3_ENET_MASK;
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addr = &imx_ccm->CCGR3;
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} else {
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@ -117,7 +120,7 @@ void enable_uart_clk(unsigned char enable)
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{
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u32 mask;
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if (is_mx6ul())
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if (is_mx6ul() || is_mx6ull())
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mask = MXC_CCM_CCGR5_UART_MASK;
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else
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mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
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@ -168,7 +171,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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reg &= ~mask;
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__raw_writel(reg, &imx_ccm->CCGR2);
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} else {
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if (is_mx6sx() || is_mx6ul()) {
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if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
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mask = MXC_CCM_CCGR6_I2C4_MASK;
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addr = &imx_ccm->CCGR6;
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} else {
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@ -279,7 +282,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
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switch (pll) {
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case PLL_BUS:
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if (!is_mx6ul()) {
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if (!is_mx6ul() && !is_mx6ull()) {
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if (pfd_num == 3) {
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/* No PFD3 on PLL2 */
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return 0;
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@ -380,7 +383,7 @@ static u32 get_ipg_per_clk(void)
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reg = __raw_readl(&imx_ccm->cscmr1);
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if (is_mx6sl() || is_mx6sx() ||
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is_mx6dqp() || is_mx6ul()) {
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is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
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if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
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return MXC_HCLK; /* OSC 24Mhz */
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}
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@ -396,7 +399,8 @@ static u32 get_uart_clk(void)
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u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
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reg = __raw_readl(&imx_ccm->cscdr1);
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if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
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if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
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is_mx6ull()) {
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if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
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freq = MXC_HCLK;
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}
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@ -415,7 +419,8 @@ static u32 get_cspi_clk(void)
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cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
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MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
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if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
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is_mx6ull()) {
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if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
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return MXC_HCLK / (cspi_podf + 1);
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}
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@ -477,7 +482,7 @@ static u32 get_mmdc_ch0_clk(void)
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u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
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if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
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if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
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podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
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@ -615,7 +620,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
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debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
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if (!is_mx6sx() && !is_mx6ul()) {
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if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
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debug("This chip not support lcd!\n");
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return;
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}
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@ -749,7 +754,7 @@ int enable_lcdif_clock(u32 base_addr)
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MXC_CCM_CCGR3_DISP_AXI_MASK) :
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(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
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MXC_CCM_CCGR3_DISP_AXI_MASK);
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} else if (is_mx6ul()) {
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} else if (is_mx6ul() || is_mx6ull()) {
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if (base_addr != LCDIF1_BASE_ADDR) {
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puts("Wrong LCD interface!\n");
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return -EINVAL;
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@ -847,7 +852,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
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reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
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} else if (fec_id == 1) {
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/* Only i.MX6SX/UL support ENET2 */
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if (!(is_mx6sx() || is_mx6ul()))
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if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
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return -EINVAL;
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reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
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reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
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@ -1069,17 +1074,27 @@ void hab_caam_clock_enable(unsigned char enable)
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{
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u32 reg;
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/* CG4 ~ CG6, CAAM clocks */
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reg = __raw_readl(&imx_ccm->CCGR0);
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if (enable)
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reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
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MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
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MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
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else
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reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
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MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
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MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
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__raw_writel(reg, &imx_ccm->CCGR0);
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if (is_mx6ull()) {
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/* CG5, DCP clock */
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reg = __raw_readl(&imx_ccm->CCGR0);
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if (enable)
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reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
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else
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reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
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__raw_writel(reg, &imx_ccm->CCGR0);
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} else {
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/* CG4 ~ CG6, CAAM clocks */
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reg = __raw_readl(&imx_ccm->CCGR0);
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if (enable)
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reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
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MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
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MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
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else
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reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
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MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
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MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
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__raw_writel(reg, &imx_ccm->CCGR0);
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}
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/* EMI slow clk */
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reg = __raw_readl(&imx_ccm->CCGR6);
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@ -379,6 +379,16 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
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/* Define the bits in register CS1CDR */
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/* MX6UL, !MX6ULL */
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#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
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#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
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#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
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#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
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#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
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#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
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#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
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#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
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#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
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#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
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#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
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@ -460,7 +470,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
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/* Define the bits in register CHSCCDR */
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#ifdef CONFIG_MX6SX
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/* i.MX6SX */
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#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
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#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
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#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
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@ -473,7 +483,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
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#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
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#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
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#else
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#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
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#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
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#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
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@ -486,7 +496,14 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
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#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
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#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
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#endif
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/* i.MX6ULL */
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#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
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#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
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#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
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#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
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#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
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#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
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#define CHSCCDR_CLK_SEL_LDB_DI0 3
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#define CHSCCDR_PODF_DIVIDE_BY_3 2
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@ -626,6 +643,12 @@ struct mxc_ccm_reg {
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/* Define the bits in registers CCGRx */
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#define MXC_CCM_CCGR_CG_MASK 3
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/* i.MX 6ULL */
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#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
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#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
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#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
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#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
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#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
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#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
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#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
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@ -702,13 +725,12 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
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#endif
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#ifndef CONFIG_MX6SX
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#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
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#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
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#else
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/* i.MX6SX/UL */
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#define MXC_CCM_CCGR2_CSI_OFFSET 2
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#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
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#endif
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#ifndef CONFIG_MX6SX
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#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
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#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
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@ -744,9 +766,18 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
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#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
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/* i.MX6ULL */
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#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
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#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
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#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
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#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
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/* Exist on i.MX6SX */
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#define MXC_CCM_CCGR3_M4_OFFSET 2
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#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
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/* i.MX6ULL */
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#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
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#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
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#define MXC_CCM_CCGR3_ENET_OFFSET 4
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#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
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#define MXC_CCM_CCGR3_QSPI_OFFSET 14
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@ -808,7 +839,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
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#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
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/* GPIO4 on i.MX6UL */
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/* GPIO4 on i.MX6UL/ULL */
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#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
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#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
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@ -817,6 +848,10 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
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#endif
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/* i.MX6ULL */
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#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
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#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
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#define MXC_CCM_CCGR4_PCIE_OFFSET 0
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#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
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/* QSPI2 on i.MX6SX */
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@ -883,6 +918,13 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
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#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
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#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
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#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
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#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
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#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
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#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
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/* i.MX6ULL */
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#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
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#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
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/* GPMI/BCH on i.MX6UL */
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#define MXC_CCM_CCGR6_BCH_OFFSET 6
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#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
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@ -895,6 +937,9 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
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#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
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#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
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/* i.MX6ULL */
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#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
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#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
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/* The following *CCGR6* exist only i.MX6SX */
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#define MXC_CCM_CCGR6_PWM8_OFFSET 16
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#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
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