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armv8: Update erratum number to align with doc

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Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.

Fixes 0cfa00cdb9 (“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Ran Wang
2021-06-16 17:53:19 +05:30
committed by Priyanka Jain
parent 13ea307f79
commit 390c73b417
2 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@@ -223,7 +223,7 @@ config ARCH_LX2162A
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1 select SYS_FSL_EC1
select SYS_FSL_EC2 select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106 select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_RGMII
@@ -255,7 +255,7 @@ config ARCH_LX2160A
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1 select SYS_FSL_EC1
select SYS_FSL_EC2 select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106 select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_RGMII
@@ -375,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798" bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A050106 config SYS_FSL_ERRATUM_A050204
bool "Workaround for USB PHY erratum A050106" bool "Workaround for USB PHY erratum A050204"
help help
USB3.0 Receiver needs to enable fixed equalization USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar for each of PHY instances in an SOC. This is similar

6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* Copyright 2014-2015 Freescale Semiconductor * Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019-2020 NXP * Copyright 2019-2021 NXP
*/ */
#include <common.h> #include <common.h>
@@ -218,7 +218,7 @@ static void erratum_a009007(void)
} }
#if defined(CONFIG_FSL_LSCH3) #if defined(CONFIG_FSL_LSCH3)
static void erratum_a050106(void) static void erratum_a050204(void)
{ {
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE; void __iomem *dcsr = (void __iomem *)DCSR_BASE;
@@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009798(); erratum_a009798();
erratum_a008997(); erratum_a008997();
erratum_a009007(); erratum_a009007();
erratum_a050106(); erratum_a050204();
#ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU /* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions. * to allow only Secure transactions.