Merge remote-tracking branch 'u-boot-marvell/master'
This commit is contained in:
Albert ARIBAUD
commit
386c6cb10d
@ -803,6 +803,7 @@ Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
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||||
Luka Perkov <uboot@lukaperkov.net>
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||||
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ib62x0 ARM926EJS
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iconnect ARM926EJS
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||||
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||||
Dave Peverley <dpeverley@mpc-data.co.uk>
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||||
@ -30,38 +30,84 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
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#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
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struct kw_sdram_bank {
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u32 win_bar;
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u32 win_sz;
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};
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struct kw_sdram_addr_dec {
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struct kw_sdram_bank sdram_bank[4];
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};
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#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
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#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
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#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
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#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
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/*
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* kw_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 kw_sdram_bar(enum memory_bank bank)
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{
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struct kw_sdram_addr_dec *base =
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(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = readl(KW_REG_CPUCS_WIN_BAR(bank));
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result = readl(&base->sdram_bank[bank].win_bar);
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return result;
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}
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/*
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* kw_sdram_bs_set - writes SDRAM Bank size
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*/
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static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
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{
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struct kw_sdram_addr_dec *base =
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(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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/* Read current register value */
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u32 reg = readl(&base->sdram_bank[bank].win_sz);
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/* Clear window size */
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reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
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/* Set new window size */
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reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
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writel(reg, &base->sdram_bank[bank].win_sz);
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}
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/*
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* kw_sdram_bs - reads SDRAM Bank size
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*/
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u32 kw_sdram_bs(enum memory_bank bank)
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{
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struct kw_sdram_addr_dec *base =
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(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
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result += 0x01000000;
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return result;
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}
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void kw_sdram_size_adjust(enum memory_bank bank)
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{
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u32 size;
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/* probe currently equipped RAM size */
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size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
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/* adjust SDRAM window size accordingly */
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kw_sdram_bs_set(bank, size);
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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@ -155,10 +155,10 @@ struct kwgpio_registers {
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/*
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* functions
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*/
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void reset_cpu(unsigned long ignored);
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unsigned char get_random_hex(void);
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unsigned int kw_sdram_bar(enum memory_bank bank);
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unsigned int kw_sdram_bs(enum memory_bank bank);
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void kw_sdram_size_adjust(enum memory_bank bank);
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int kw_config_adr_windows(void);
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void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
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unsigned int gpp0_oe, unsigned int gpp1_oe);
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@ -85,7 +85,7 @@
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#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
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#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
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#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
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#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
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#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
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#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
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#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
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@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers {
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/*
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* functions
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*/
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void reset_cpu(unsigned long ignored);
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u32 orion5x_device_id(void);
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u32 orion5x_device_rev(void);
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unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
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@ -13,10 +13,11 @@
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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#define MII_MARVELL_PHY_PAGE 22
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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@ -31,15 +32,44 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr)
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1116 Initialized on %s\n", name);
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}
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void mv_phy_88e1318_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Set control mode 4 for LED[0].
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
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miiphy_read(name, phyaddr, 16, ®);
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reg |= 0xf;
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miiphy_write(name, phyaddr, 16, reg);
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1318 Initialized on %s\n", name);
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}
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#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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@ -12,6 +12,7 @@
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr);
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void mv_phy_88e1318_init(const char *name, u16 phyaddr);
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#endif
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac);
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162
board/LaCie/netspace_v2/kwbimage-ns2l.cfg
Normal file
162
board/LaCie/netspace_v2/kwbimage-ns2l.cfg
Normal file
@ -0,0 +1,162 @@
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1B1B1B9B
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000618 # DDR Configuration register
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# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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|
||||
DATA 0xFFD01410 0x0000DDDD # DDR Address Control
|
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# bit1-0: 00, Cs0width=x8
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# bit3-2: 10, Cs0size=512Mb
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# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
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||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
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||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
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||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
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||||
# bit31-1: 0 required
|
||||
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DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
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||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@ -107,7 +107,11 @@ int misc_init_r(void)
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
|
||||
mv_phy_88e1318_init("egiga0", 0);
|
||||
#else
|
||||
mv_phy_88e1116_init("egiga0", 8);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -195,9 +195,11 @@ int board_init(void)
|
||||
static void check_power_switch(void)
|
||||
{
|
||||
if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
|
||||
/* turn off HDD and USB power */
|
||||
/* turn off fan, HDD and USB power */
|
||||
kw_gpio_set_value(GPIO_HDD_POWER, 0);
|
||||
kw_gpio_set_value(GPIO_USB_VBUS, 0);
|
||||
kw_gpio_set_value(GPIO_FAN_HIGH, 1);
|
||||
kw_gpio_set_value(GPIO_FAN_LOW, 1);
|
||||
set_led(LED_OFF);
|
||||
|
||||
/* loop until released */
|
||||
@ -207,6 +209,8 @@ static void check_power_switch(void)
|
||||
/* turn power on again */
|
||||
kw_gpio_set_value(GPIO_HDD_POWER, 1);
|
||||
kw_gpio_set_value(GPIO_USB_VBUS, 1);
|
||||
kw_gpio_set_value(GPIO_FAN_HIGH, 0);
|
||||
kw_gpio_set_value(GPIO_FAN_LOW, 0);
|
||||
set_led(LED_POWER_BLINKING);
|
||||
}
|
||||
}
|
||||
|
||||
43
board/iomega/iconnect/Makefile
Normal file
43
board/iomega/iconnect/Makefile
Normal file
@ -0,0 +1,43 @@
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := iconnect.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
107
board/iomega/iconnect/iconnect.c
Normal file
107
board/iomega/iconnect/iconnect.c
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <uboot@lukaperkov.net>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "iconnect.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
kw_config_gpio(ICONNECT_OE_VAL_LOW,
|
||||
ICONNECT_OE_VAL_HIGH,
|
||||
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn, /* Reset signal */
|
||||
MPP7_GPO,
|
||||
MPP8_TW_SDA, /* I2C */
|
||||
MPP9_TW_SCK, /* I2C */
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO, /* Reset button */
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0,
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GPIO,
|
||||
MPP29_GPIO,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GE1_14,
|
||||
MPP35_GPIO, /* OTB button */
|
||||
MPP36_AUDIO_SPDIFI,
|
||||
MPP37_AUDIO_SPDIFO,
|
||||
MPP38_GPIO,
|
||||
MPP39_TDM_SPI_CS0,
|
||||
MPP40_TDM_SPI_SCK,
|
||||
MPP41_GPIO, /* LED brightness */
|
||||
MPP42_GPIO, /* LED power (blue) */
|
||||
MPP43_GPIO, /* LED power (red) */
|
||||
MPP44_GPIO, /* LED USB 1 */
|
||||
MPP45_GPIO, /* LED USB 2 */
|
||||
MPP46_GPIO, /* LED USB 3 */
|
||||
MPP47_GPIO, /* LED USB 4 */
|
||||
MPP48_GPIO, /* LED OTB */
|
||||
MPP49_GPIO,
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
39
board/iomega/iconnect/iconnect.h
Normal file
39
board/iomega/iconnect/iconnect.h
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <uboot@lukaperkov.net>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __ICONNECT_H
|
||||
#define __ICONNECT_H
|
||||
|
||||
#define ICONNECT_OE_LOW (~(1 << 7))
|
||||
#define ICONNECT_OE_HIGH (~(1 << 10))
|
||||
#define ICONNECT_OE_VAL_LOW (0)
|
||||
#define ICONNECT_OE_VAL_HIGH (1 << 10)
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __ICONNECT_H */
|
||||
165
board/iomega/iconnect/kwbimage.cfg
Normal file
165
board/iomega/iconnect/kwbimage.cfg
Normal file
@ -0,0 +1,165 @@
|
||||
#
|
||||
# (C) Copyright 2009-2012
|
||||
# Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
# Luka Perkov <uboot@lukaperkov.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
|
||||
NAND_ECC_MODE default
|
||||
NAND_PAGE_SIZE 0x0800
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xffd100e0 0x1b1b1b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xffd01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: 0x0,
|
||||
# bit24: 0x1, enable exit self refresh mode on DDR access
|
||||
# bit25: 0x1, required
|
||||
# bit29-26: 0x0,
|
||||
# bit31-30: 0x1,
|
||||
|
||||
DATA 0xffd01404 0x37543000 # DDR Controller Control Low
|
||||
# bit4: 0x0, addr/cmd in smame cycle
|
||||
# bit5: 0x0, clk is driven during self refresh, we don't care for APX
|
||||
# bit6: 0x0, use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0x0, input buffer always powered up
|
||||
# bit18: 0x1, cpu lock transaction enabled
|
||||
# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 0x3, required
|
||||
# bit31: 0x0, no additional STARTBURST delay
|
||||
|
||||
DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11-8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: 0x0, required
|
||||
|
||||
DATA 0xffd01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 00, Cs0width (x8)
|
||||
# bit3-2: 11, Cs0size (1Gb)
|
||||
# bit5-4: 00, Cs1width (x8)
|
||||
# bit7-6: 11, Cs1size (1Gb)
|
||||
# bit9-8: 00, Cs2width (nonexistent)
|
||||
# bit11-10: 00, Cs2size (nonexistent)
|
||||
# bit13-12: 00, Cs3width (nonexistent)
|
||||
# bit15-14: 00, Cs3size (nonexistent)
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0x0, required
|
||||
|
||||
DATA 0xffd01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0x0, required
|
||||
|
||||
DATA 0xffd01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0x0, required
|
||||
|
||||
DATA 0xffd0141c 0x00000c52 # DDR Mode
|
||||
# bit2-0: 0x2, BurstLen=2 required
|
||||
# bit3: 0x0, BurstType=0 required
|
||||
# bit6-4: 0x4, CL=5
|
||||
# bit7: 0x0, TestMode=0 normal
|
||||
# bit8: 0x0, DLL reset=0 normal
|
||||
# bit11-9: 0x6, auto-precharge write recovery ????????????
|
||||
# bit12: 0x0, PD must be zero
|
||||
# bit31-13: 0x0, required
|
||||
|
||||
DATA 0xffd01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 0x0, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 0x0, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0x0, required
|
||||
|
||||
DATA 0xffd01424 0x0000f17f # DDR Controller Control High
|
||||
# bit2-0: 0x7, required
|
||||
# bit3: 0x1, MBUS Burst Chop disabled
|
||||
# bit6-4: 0x7, required
|
||||
# bit7: 0x0,
|
||||
# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9: 0x0, no half clock cycle addition to dataout
|
||||
# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 0xf, required
|
||||
# bit31-16: 0x0, required
|
||||
|
||||
DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
|
||||
# bit0: 0x1, Window enabled
|
||||
# bit1: 0x0, Write Protect disabled
|
||||
# bit3-2: 0x0, CS0 hit selected
|
||||
# bit23-4: 0xfffff, required
|
||||
# bit31-24: 0x0f, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
|
||||
|
||||
DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
|
||||
# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
|
||||
# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
|
||||
# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 0x1, ODT1 active NEVER!
|
||||
# bit31-4: 0x0, required
|
||||
|
||||
DATA 0xffd0149c 0x0000e803 # CPU ODT Control
|
||||
DATA 0xffd01480 0x00000001 # DDR Initialization Control
|
||||
# bit0: 0x1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@ -250,7 +250,8 @@ int board_early_init_f(void)
|
||||
tmp = readl(KW_GPIO0_BASE + 4);
|
||||
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
|
||||
#endif
|
||||
|
||||
/* adjust SDRAM size for bank 0 */
|
||||
kw_sdram_size_adjust(0);
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
@ -365,6 +366,71 @@ void reset_phy(void)
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
|
||||
}
|
||||
#elif defined(CONFIG_KM_PIGGY4_88E6352)
|
||||
|
||||
#include <mv88e6352.h>
|
||||
|
||||
#if defined(CONFIG_KM_NUSA)
|
||||
struct mv88e_sw_reg extsw_conf[] = {
|
||||
/*
|
||||
* port 0, PIGGY4, autoneg
|
||||
* first the fix for the 1000Mbits Autoneg, this is from
|
||||
* a Marvell errata, the regs are undocumented
|
||||
*/
|
||||
{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
|
||||
{ PHY(0), PHY_STATUS, AN1000FIX },
|
||||
{ PHY(0), PHY_PAGE, 0 },
|
||||
/* now the real port and phy configuration */
|
||||
{ PORT(0), PORT_PHY, NO_SPEED_FOR },
|
||||
{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
|
||||
{ PHY(0), PHY_1000_CTRL, NO_ADV },
|
||||
{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
|
||||
{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
|
||||
FULL_DUPLEX },
|
||||
/* port 1, unused */
|
||||
{ PORT(1), PORT_CTRL, PORT_DIS },
|
||||
{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
|
||||
{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
|
||||
/* port 2, unused */
|
||||
{ PORT(2), PORT_CTRL, PORT_DIS },
|
||||
{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
|
||||
{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
|
||||
/* port 3, unused */
|
||||
{ PORT(3), PORT_CTRL, PORT_DIS },
|
||||
{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
|
||||
{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
|
||||
/* port 4, ICNEV, SerDes, SGMII */
|
||||
{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
|
||||
{ PORT(4), PORT_PHY, SPEED_1000_FOR },
|
||||
{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
|
||||
{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
|
||||
{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
|
||||
/* port 5, CPU_RGMII */
|
||||
{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
|
||||
FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
|
||||
FULL_DPX_FOR | SPEED_1000_FOR },
|
||||
{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
|
||||
/* port 6, unused, this port has no phy */
|
||||
{ PORT(6), PORT_CTRL, PORT_DIS },
|
||||
};
|
||||
#else
|
||||
struct mv88e_sw_reg extsw_conf[] = {};
|
||||
#endif
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_KM_MVEXTSW_ADDR)
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
|
||||
ARRAY_SIZE(extsw_conf));
|
||||
mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
/* Configure and enable MV88E1118 PHY on the piggy*/
|
||||
void reset_phy(void)
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
@ -41,6 +42,8 @@ int board_early_init_f(void)
|
||||
IB62x0_OE_VAL_HIGH,
|
||||
IB62x0_OE_LOW, IB62x0_OE_HIGH);
|
||||
|
||||
/* Set SATA activity LEDs to default off */
|
||||
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
|
||||
@ -37,4 +37,8 @@
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
/* SATAHC related */
|
||||
#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C)
|
||||
#define MVSATAHC_LED_POLARITY_CTRL (1 << 3)
|
||||
|
||||
#endif /* __IB62x0_H */
|
||||
|
||||
@ -152,6 +152,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw
|
||||
calimain arm arm926ejs calimain omicron davinci
|
||||
pogo_e02 arm arm926ejs - cloudengines kirkwood
|
||||
dns325 arm arm926ejs - d-link kirkwood
|
||||
iconnect arm arm926ejs - iomega kirkwood
|
||||
lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
|
||||
lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
|
||||
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
|
||||
@ -160,9 +161,12 @@ kmnusa arm arm926ejs km_arm keymile
|
||||
mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
|
||||
kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
|
||||
portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
|
||||
d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2
|
||||
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
|
||||
net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
|
||||
netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2
|
||||
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
|
||||
netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
|
||||
netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
|
||||
dreamplug arm arm926ejs - Marvell kirkwood
|
||||
guruplug arm arm926ejs - Marvell kirkwood
|
||||
|
||||
@ -222,7 +222,7 @@
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
|
||||
|
||||
/*
|
||||
* Other required minimal configurations
|
||||
|
||||
129
include/configs/iconnect.h
Normal file
129
include/configs/iconnect.h
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* (C) Copyright 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <uboot@lukaperkov.net>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_ICONNECT_H
|
||||
#define _CONFIG_ICONNECT_H
|
||||
|
||||
/*
|
||||
* Version number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING " Iomega iConnect"
|
||||
|
||||
/*
|
||||
* High level configuration options
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 /* SOC Name */
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
* Machine type
|
||||
*/
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
|
||||
|
||||
/*
|
||||
* Compression configuration
|
||||
*/
|
||||
#define CONFIG_BZIP2
|
||||
#define CONFIG_LZMA
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
|
||||
#define CONFIG_SYS_MVFS
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
#undef CONFIG_SYS_PROMPT
|
||||
#define CONFIG_SYS_PROMPT "iconnect => "
|
||||
|
||||
/*
|
||||
* Environment variables configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#define CONFIG_ENV_OFFSET 0x80000
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
|
||||
"ubi part rootfs; " \
|
||||
"ubifsmount rootfs; " \
|
||||
"ubifsload 0x800000 ${kernel}; " \
|
||||
"bootm 0x800000"
|
||||
|
||||
#define CONFIG_MTDPARTS \
|
||||
"mtdparts=orion_nand:" \
|
||||
"0x80000@0x0(uboot)," \
|
||||
"0x20000@0x80000(uboot_env)," \
|
||||
"-@0xa0000(rootfs)\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=console=ttyS0,115200\0" \
|
||||
"mtdids=nand0=orion_nand\0" \
|
||||
"mtdparts="CONFIG_MTDPARTS \
|
||||
"kernel=/boot/uImage\0" \
|
||||
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
|
||||
|
||||
/*
|
||||
* Ethernet driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 11
|
||||
#undef CONFIG_RESET_PHY_R
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
|
||||
#endif /* _CONFIG_ICONNECT_H */
|
||||
@ -62,6 +62,8 @@
|
||||
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
|
||||
#define CONFIG_KM_FPGA_CONFIG
|
||||
#define CONFIG_KM_PIGGY4_88E6352
|
||||
#define CONFIG_MV88E6352_SWITCH
|
||||
#define CONFIG_KM_MVEXTSW_ADDR 0x10
|
||||
|
||||
/* KM_MGCOGE3UN */
|
||||
#elif defined(CONFIG_KM_MGCOGE3UN)
|
||||
|
||||
@ -27,9 +27,20 @@
|
||||
#elif defined(CONFIG_NETSPACE_V2)
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
|
||||
#define CONFIG_IDENT_STRING " NS v2"
|
||||
#elif defined(CONFIG_NETSPACE_LITE_V2)
|
||||
#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
|
||||
#define CONFIG_IDENT_STRING " NS v2 Lite"
|
||||
#elif defined(CONFIG_NETSPACE_MINI_V2)
|
||||
#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
|
||||
#define CONFIG_IDENT_STRING " NS v2 Mini"
|
||||
#elif defined(CONFIG_NETSPACE_MAX_V2)
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
|
||||
#define CONFIG_IDENT_STRING " NS Max v2"
|
||||
#elif defined(CONFIG_D2NET_V2)
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
|
||||
#define CONFIG_IDENT_STRING " D2 v2"
|
||||
#elif defined(CONFIG_NET2BIG_V2)
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
|
||||
#define CONFIG_IDENT_STRING " 2Big v2"
|
||||
@ -41,8 +52,13 @@
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 /* SOC Name */
|
||||
#define CONFIG_KIRKWOOD /* SoC Family Name */
|
||||
/* SoC name */
|
||||
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
|
||||
#define CONFIG_KW88F6192
|
||||
#else
|
||||
#define CONFIG_KW88F6281
|
||||
#endif
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
@ -56,7 +72,9 @@
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IDE
|
||||
#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
|
||||
#define CONFIG_CMD_USB
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Core clock definition
|
||||
@ -68,9 +86,14 @@
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#ifdef CONFIG_INETSPACE_V2
|
||||
/* Different SDRAM configuration and size for Internet Space v2 */
|
||||
/*
|
||||
* Different SDRAM configuration and size for some of the boards derived
|
||||
* from the Network Space v2
|
||||
*/
|
||||
#if defined(CONFIG_INETSPACE_V2)
|
||||
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
|
||||
#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
|
||||
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -88,7 +111,9 @@
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1
|
||||
#if defined(CONFIG_NET2BIG_V2)
|
||||
#if defined(CONFIG_D2NET_V2)
|
||||
#define CONFIG_SYS_PROMPT "d2v2> "
|
||||
#elif defined(CONFIG_NET2BIG_V2)
|
||||
#define CONFIG_SYS_PROMPT "2big2> "
|
||||
#else
|
||||
#define CONFIG_SYS_PROMPT "ns2> "
|
||||
@ -108,7 +133,8 @@
|
||||
*/
|
||||
#ifdef CONFIG_MVSATA_IDE
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
||||
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2)
|
||||
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
|
||||
defined(CONFIG_NET2BIG_V2)
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
|
||||
#endif
|
||||
#endif /* CONFIG_MVSATA_IDE */
|
||||
@ -129,6 +155,12 @@
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
|
||||
#endif /* CONFIG_CMD_I2C */
|
||||
|
||||
/*
|
||||
* Partition support
|
||||
*/
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
|
||||
/*
|
||||
* File systems support
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user