usb:gadget:s5p USB Device Controller (UDC) implementation
This commit provides UDC driver support for Samsung's SoC family of processors. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Remy Bohmer <linux@bohmer.net>
This commit is contained in:
Lukasz Majewski
Remy Bohmer
parent
5f4b4f2fed
commit
38517a7821
@ -26,6 +26,10 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libusb_gadget.o
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# new USB gadget layer dependencies
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ifdef CONFIG_USB_GADGET
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COBJS-y += epautoconf.o config.o usbstring.o
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COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
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endif
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ifdef CONFIG_USB_ETHER
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COBJS-y += ether.o epautoconf.o config.o usbstring.o
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COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
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271
drivers/usb/gadget/regs-otg.h
Normal file
271
drivers/usb/gadget/regs-otg.h
Normal file
@ -0,0 +1,271 @@
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/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
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*
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* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
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*
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* Registers remapping:
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* Lukasz Majewski <l.majewski@samsumg.com>
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*
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* This include file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
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#define __ASM_ARCH_REGS_USB_OTG_HS_H
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/* USB2.0 OTG Controller register */
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struct s3c_usbotg_phy {
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u32 phypwr;
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u32 phyclk;
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u32 rstcon;
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};
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/* Device Logical IN Endpoint-Specific Registers */
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struct s3c_dev_in_endp {
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u32 diepctl;
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u8 res1[4];
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u32 diepint;
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u8 res2[4];
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u32 dieptsiz;
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u32 diepdma;
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u8 res3[4];
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u32 diepdmab;
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};
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/* Device Logical OUT Endpoint-Specific Registers */
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struct s3c_dev_out_endp {
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u32 doepctl;
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u8 res1[4];
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u32 doepint;
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u8 res2[4];
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u32 doeptsiz;
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u32 doepdma;
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u8 res3[4];
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u32 doepdmab;
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};
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struct ep_fifo {
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u32 fifo;
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u8 res[4092];
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};
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/* USB2.0 OTG Controller register */
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struct s3c_usbotg_reg {
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/* Core Global Registers */
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u32 gotgctl; /* OTG Control & Status */
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u32 gotgint; /* OTG Interrupt */
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u32 gahbcfg; /* Core AHB Configuration */
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u32 gusbcfg; /* Core USB Configuration */
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u32 grstctl; /* Core Reset */
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u32 gintsts; /* Core Interrupt */
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u32 gintmsk; /* Core Interrupt Mask */
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u32 grxstsr; /* Receive Status Debug Read/Status Read */
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u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
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u32 grxfsiz; /* Receive FIFO Size */
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u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
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u8 res1[216];
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u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
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u8 res2[1728];
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/* Device Configuration */
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u32 dcfg; /* Device Configuration Register */
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u32 dctl; /* Device Control */
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u32 dsts; /* Device Status */
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u8 res3[4];
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u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
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u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
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u32 daint; /* Device All Endpoints Interrupt */
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u32 daintmsk; /* Device All Endpoints Interrupt Mask */
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u8 res4[224];
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struct s3c_dev_in_endp in_endp[16];
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struct s3c_dev_out_endp out_endp[16];
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u8 res5[768];
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struct ep_fifo ep[16];
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};
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/*===================================================================== */
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/*definitions related to CSR setting */
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/* S3C_UDC_OTG_GOTGCTL */
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#define B_SESSION_VALID (0x1<<19)
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#define A_SESSION_VALID (0x1<<18)
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/* S3C_UDC_OTG_GAHBCFG */
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#define PTXFE_HALF (0<<8)
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#define PTXFE_ZERO (1<<8)
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#define NPTXFE_HALF (0<<7)
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#define NPTXFE_ZERO (1<<7)
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#define MODE_SLAVE (0<<5)
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#define MODE_DMA (1<<5)
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#define BURST_SINGLE (0<<1)
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#define BURST_INCR (1<<1)
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#define BURST_INCR4 (3<<1)
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#define BURST_INCR8 (5<<1)
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#define BURST_INCR16 (7<<1)
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#define GBL_INT_UNMASK (1<<0)
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#define GBL_INT_MASK (0<<0)
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/* S3C_UDC_OTG_GRSTCTL */
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#define AHB_MASTER_IDLE (1u<<31)
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#define CORE_SOFT_RESET (0x1<<0)
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/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
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#define INT_RESUME (1u<<31)
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#define INT_DISCONN (0x1<<29)
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#define INT_CONN_ID_STS_CNG (0x1<<28)
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#define INT_OUT_EP (0x1<<19)
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#define INT_IN_EP (0x1<<18)
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#define INT_ENUMDONE (0x1<<13)
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#define INT_RESET (0x1<<12)
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#define INT_SUSPEND (0x1<<11)
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#define INT_EARLY_SUSPEND (0x1<<10)
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#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
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#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
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#define INT_SOF (0x1<<3)
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#define INT_DEV_MODE (0x0<<0)
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#define INT_HOST_MODE (0x1<<1)
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#define INT_GOUTNakEff (0x01<<7)
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#define INT_GINNakEff (0x01<<6)
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#define FULL_SPEED_CONTROL_PKT_SIZE 8
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#define FULL_SPEED_BULK_PKT_SIZE 64
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#define HIGH_SPEED_CONTROL_PKT_SIZE 64
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#define HIGH_SPEED_BULK_PKT_SIZE 512
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#define RX_FIFO_SIZE (1024*4)
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#define NPTX_FIFO_SIZE (1024*4)
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#define PTX_FIFO_SIZE (1536*1)
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#define DEPCTL_TXFNUM_0 (0x0<<22)
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#define DEPCTL_TXFNUM_1 (0x1<<22)
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#define DEPCTL_TXFNUM_2 (0x2<<22)
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#define DEPCTL_TXFNUM_3 (0x3<<22)
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#define DEPCTL_TXFNUM_4 (0x4<<22)
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/* Enumeration speed */
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#define USB_HIGH_30_60MHZ (0x0<<1)
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#define USB_FULL_30_60MHZ (0x1<<1)
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#define USB_LOW_6MHZ (0x2<<1)
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#define USB_FULL_48MHZ (0x3<<1)
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/* S3C_UDC_OTG_GRXSTSP STATUS */
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#define OUT_PKT_RECEIVED (0x2<<17)
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#define OUT_TRANSFER_COMPLELTED (0x3<<17)
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#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
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#define SETUP_PKT_RECEIVED (0x6<<17)
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#define GLOBAL_OUT_NAK (0x1<<17)
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/* S3C_UDC_OTG_DCTL device control register */
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#define NORMAL_OPERATION (0x1<<0)
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#define SOFT_DISCONNECT (0x1<<1)
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/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
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#define DAINT_OUT_BIT (16)
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#define DAINT_MASK (0xFFFF)
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/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
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control IN/OUT endpoint 0 control register */
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#define DEPCTL_EPENA (0x1<<31)
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#define DEPCTL_EPDIS (0x1<<30)
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#define DEPCTL_SETD1PID (0x1<<29)
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#define DEPCTL_SETD0PID (0x1<<28)
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#define DEPCTL_SNAK (0x1<<27)
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#define DEPCTL_CNAK (0x1<<26)
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#define DEPCTL_STALL (0x1<<21)
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#define DEPCTL_TYPE_BIT (18)
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#define DEPCTL_TYPE_MASK (0x3<<18)
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#define DEPCTL_CTRL_TYPE (0x0<<18)
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#define DEPCTL_ISO_TYPE (0x1<<18)
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#define DEPCTL_BULK_TYPE (0x2<<18)
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#define DEPCTL_INTR_TYPE (0x3<<18)
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#define DEPCTL_USBACTEP (0x1<<15)
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#define DEPCTL_NEXT_EP_BIT (11)
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#define DEPCTL_MPS_BIT (0)
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#define DEPCTL_MPS_MASK (0x7FF)
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#define DEPCTL0_MPS_64 (0x0<<0)
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#define DEPCTL0_MPS_32 (0x1<<0)
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#define DEPCTL0_MPS_16 (0x2<<0)
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#define DEPCTL0_MPS_8 (0x3<<0)
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#define DEPCTL_MPS_BULK_512 (512<<0)
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#define DEPCTL_MPS_INT_MPS_16 (16<<0)
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#define DIEPCTL0_NEXT_EP_BIT (11)
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/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
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common interrupt mask register */
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/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
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#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
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#define INTKNEPMIS (0x1<<5)
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#define INTKN_TXFEMP (0x1<<4)
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#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
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#define AHB_ERROR (0x1<<2)
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#define EPDISBLD (0x1<<1)
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#define TRANSFER_DONE (0x1<<0)
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#define USB_PHY_CTRL_EN0 (0x1 << 0)
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/* OPHYPWR */
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#define PHY_0_SLEEP (0x1 << 5)
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#define OTG_DISABLE_0 (0x1 << 4)
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#define ANALOG_PWRDOWN (0x1 << 3)
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#define FORCE_SUSPEND_0 (0x1 << 0)
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/* URSTCON */
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#define HOST_SW_RST (0x1 << 4)
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#define PHY_SW_RST1 (0x1 << 3)
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#define PHYLNK_SW_RST (0x1 << 2)
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#define LINK_SW_RST (0x1 << 1)
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#define PHY_SW_RST0 (0x1 << 0)
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/* OPHYCLK */
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#define COMMON_ON_N1 (0x1 << 7)
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#define COMMON_ON_N0 (0x1 << 4)
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#define ID_PULLUP0 (0x1 << 2)
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#define CLK_SEL_24MHZ (0x3 << 0)
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#define CLK_SEL_12MHZ (0x2 << 0)
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#define CLK_SEL_48MHZ (0x0 << 0)
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/* Device Configuration Register DCFG */
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#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
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#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
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#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
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#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
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#define EP_MISS_CNT(x) (x << 18)
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#define DEVICE_ADDRESS(x) (x << 4)
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/* Core Reset Register (GRSTCTL) */
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#define TX_FIFO_FLUSH (0x1 << 5)
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#define RX_FIFO_FLUSH (0x1 << 4)
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#define TX_FIFO_NUMBER(x) (x << 6)
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#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
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/* Masks definitions */
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#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
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| INT_RESET | INT_SUSPEND)
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#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
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#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
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#define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
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| GBL_INT_UNMASK)
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/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
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#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
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/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
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#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
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/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
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#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
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#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
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/* Device ALL Endpoints Interrupt Register (DAINT) */
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#define DAINT_IN_EP_INT(x) (x << 0)
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#define DAINT_OUT_EP_INT(x) (x << 16)
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#endif
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892
drivers/usb/gadget/s3c_udc_otg.c
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892
drivers/usb/gadget/s3c_udc_otg.c
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@ -0,0 +1,892 @@
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/*
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* drivers/usb/gadget/s3c_udc_otg.c
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* Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
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*
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* Copyright (C) 2008 for Samsung Electronics
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*
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* BSP Support for Samsung's UDC driver
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* available at:
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* git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
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*
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* State machine bugfixes:
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* Marek Szyprowski <m.szyprowski@samsung.com>
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*
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* Ported to u-boot:
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* Marek Szyprowski <m.szyprowski@samsung.com>
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* Lukasz Majewski <l.majewski@samsumg.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <linux/list.h>
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#include <malloc.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/gpio.h>
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#include "regs-otg.h"
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#include <usb/s3c_udc.h>
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#include <usb/lin_gadget_compat.h>
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/***********************************************************/
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#define OTG_DMA_MODE 1
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#undef DEBUG_S3C_UDC_SETUP
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#undef DEBUG_S3C_UDC_EP0
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#undef DEBUG_S3C_UDC_ISR
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#undef DEBUG_S3C_UDC_OUT_EP
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#undef DEBUG_S3C_UDC_IN_EP
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#undef DEBUG_S3C_UDC
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/* #define DEBUG_S3C_UDC_SETUP */
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/* #define DEBUG_S3C_UDC_EP0 */
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/* #define DEBUG_S3C_UDC_ISR */
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/* #define DEBUG_S3C_UDC_OUT_EP */
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/* #define DEBUG_S3C_UDC_IN_EP */
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/* #define DEBUG_S3C_UDC */
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#include <usb/s3c_udc.h>
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#define EP0_CON 0
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#define EP_MASK 0xF
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#if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_ISR) \
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|| defined(DEBUG_S3C_UDC_OUT_EP)
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static char *state_names[] = {
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"WAIT_FOR_SETUP",
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"DATA_STATE_XMIT",
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"DATA_STATE_NEED_ZLP",
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"WAIT_FOR_OUT_STATUS",
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"DATA_STATE_RECV",
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"WAIT_FOR_COMPLETE",
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"WAIT_FOR_OUT_COMPLETE",
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"WAIT_FOR_IN_COMPLETE",
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"WAIT_FOR_NULL_COMPLETE",
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};
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#endif
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#define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
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#define DRIVER_VERSION "15 March 2009"
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struct s3c_udc *the_controller;
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static const char driver_name[] = "s3c-udc";
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static const char driver_desc[] = DRIVER_DESC;
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static const char ep0name[] = "ep0-control";
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/* Max packet size*/
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static unsigned int ep0_fifo_size = 64;
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static unsigned int ep_fifo_size = 512;
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static unsigned int ep_fifo_size2 = 1024;
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static int reset_available = 1;
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|
||||
static struct usb_ctrlrequest *usb_ctrl;
|
||||
static dma_addr_t usb_ctrl_dma_addr;
|
||||
|
||||
/*
|
||||
Local declarations.
|
||||
*/
|
||||
static int s3c_ep_enable(struct usb_ep *ep,
|
||||
const struct usb_endpoint_descriptor *);
|
||||
static int s3c_ep_disable(struct usb_ep *ep);
|
||||
static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
|
||||
gfp_t gfp_flags);
|
||||
static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
|
||||
|
||||
static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
|
||||
static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
|
||||
static int s3c_fifo_status(struct usb_ep *ep);
|
||||
static void s3c_fifo_flush(struct usb_ep *ep);
|
||||
static void s3c_ep0_read(struct s3c_udc *dev);
|
||||
static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
|
||||
static void s3c_handle_ep0(struct s3c_udc *dev);
|
||||
static int s3c_ep0_write(struct s3c_udc *dev);
|
||||
static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
|
||||
static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
|
||||
static void stop_activity(struct s3c_udc *dev,
|
||||
struct usb_gadget_driver *driver);
|
||||
static int udc_enable(struct s3c_udc *dev);
|
||||
static void udc_set_address(struct s3c_udc *dev, unsigned char address);
|
||||
static void reconfig_usbd(void);
|
||||
static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
|
||||
static void nuke(struct s3c_ep *ep, int status);
|
||||
static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
|
||||
static void s3c_udc_set_nak(struct s3c_ep *ep);
|
||||
|
||||
static struct usb_ep_ops s3c_ep_ops = {
|
||||
.enable = s3c_ep_enable,
|
||||
.disable = s3c_ep_disable,
|
||||
|
||||
.alloc_request = s3c_alloc_request,
|
||||
.free_request = s3c_free_request,
|
||||
|
||||
.queue = s3c_queue,
|
||||
.dequeue = s3c_dequeue,
|
||||
|
||||
.set_halt = s3c_udc_set_halt,
|
||||
.fifo_status = s3c_fifo_status,
|
||||
.fifo_flush = s3c_fifo_flush,
|
||||
};
|
||||
|
||||
#define create_proc_files() do {} while (0)
|
||||
#define remove_proc_files() do {} while (0)
|
||||
|
||||
/***********************************************************/
|
||||
|
||||
void __iomem *regs_otg;
|
||||
struct s3c_usbotg_reg *reg;
|
||||
struct s3c_usbotg_phy *phy;
|
||||
static unsigned int usb_phy_ctrl;
|
||||
|
||||
void otg_phy_init(struct s3c_udc *dev)
|
||||
{
|
||||
dev->pdata->phy_control(1);
|
||||
|
||||
/*USB PHY0 Enable */
|
||||
printf("USB PHY0 Enable\n");
|
||||
|
||||
/* Enable PHY */
|
||||
writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
|
||||
|
||||
if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
|
||||
writel((readl(&phy->phypwr)
|
||||
&~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
|
||||
&~FORCE_SUSPEND_0), &phy->phypwr);
|
||||
else /* C110 GONI */
|
||||
writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
|
||||
&~FORCE_SUSPEND_0), &phy->phypwr);
|
||||
|
||||
writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
|
||||
CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
|
||||
|
||||
writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
|
||||
| PHY_SW_RST0, &phy->rstcon);
|
||||
udelay(10);
|
||||
writel(readl(&phy->rstcon)
|
||||
&~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
void otg_phy_off(struct s3c_udc *dev)
|
||||
{
|
||||
/* reset controller just in case */
|
||||
writel(PHY_SW_RST0, &phy->rstcon);
|
||||
udelay(20);
|
||||
writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
|
||||
udelay(20);
|
||||
|
||||
writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
|
||||
| FORCE_SUSPEND_0, &phy->phypwr);
|
||||
|
||||
writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
|
||||
|
||||
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
|
||||
&phy->phyclk);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
dev->pdata->phy_control(0);
|
||||
}
|
||||
|
||||
/***********************************************************/
|
||||
|
||||
#include "s3c_udc_otg_xfer_dma.c"
|
||||
|
||||
/*
|
||||
* udc_disable - disable USB device controller
|
||||
*/
|
||||
static void udc_disable(struct s3c_udc *dev)
|
||||
{
|
||||
DEBUG_SETUP("%s: %p\n", __func__, dev);
|
||||
|
||||
udc_set_address(dev, 0);
|
||||
|
||||
dev->ep0state = WAIT_FOR_SETUP;
|
||||
dev->gadget.speed = USB_SPEED_UNKNOWN;
|
||||
dev->usb_address = 0;
|
||||
|
||||
otg_phy_off(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* udc_reinit - initialize software state
|
||||
*/
|
||||
static void udc_reinit(struct s3c_udc *dev)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
DEBUG_SETUP("%s: %p\n", __func__, dev);
|
||||
|
||||
/* device/ep0 records init */
|
||||
INIT_LIST_HEAD(&dev->gadget.ep_list);
|
||||
INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
|
||||
dev->ep0state = WAIT_FOR_SETUP;
|
||||
|
||||
/* basic endpoint records init */
|
||||
for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
|
||||
struct s3c_ep *ep = &dev->ep[i];
|
||||
|
||||
if (i != 0)
|
||||
list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
|
||||
|
||||
ep->desc = 0;
|
||||
ep->stopped = 0;
|
||||
INIT_LIST_HEAD(&ep->queue);
|
||||
ep->pio_irqs = 0;
|
||||
}
|
||||
|
||||
/* the rest was statically initialized, and is read-only */
|
||||
}
|
||||
|
||||
#define BYTES2MAXP(x) (x / 8)
|
||||
#define MAXP2BYTES(x) (x * 8)
|
||||
|
||||
/* until it's enabled, this UDC should be completely invisible
|
||||
* to any USB host.
|
||||
*/
|
||||
static int udc_enable(struct s3c_udc *dev)
|
||||
{
|
||||
DEBUG_SETUP("%s: %p\n", __func__, dev);
|
||||
|
||||
otg_phy_init(dev);
|
||||
reconfig_usbd();
|
||||
|
||||
DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
|
||||
readl(®->gintmsk));
|
||||
|
||||
dev->gadget.speed = USB_SPEED_UNKNOWN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Register entry point for the peripheral controller driver.
|
||||
*/
|
||||
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
|
||||
{
|
||||
struct s3c_udc *dev = the_controller;
|
||||
int retval = 0;
|
||||
unsigned long flags;
|
||||
|
||||
DEBUG_SETUP("%s: %s\n", __func__, "no name");
|
||||
|
||||
if (!driver
|
||||
|| (driver->speed != USB_SPEED_FULL
|
||||
&& driver->speed != USB_SPEED_HIGH)
|
||||
|| !driver->bind || !driver->disconnect || !driver->setup)
|
||||
return -EINVAL;
|
||||
if (!dev)
|
||||
return -ENODEV;
|
||||
if (dev->driver)
|
||||
return -EBUSY;
|
||||
|
||||
spin_lock_irqsave(&dev->lock, flags);
|
||||
/* first hook up the driver ... */
|
||||
dev->driver = driver;
|
||||
spin_unlock_irqrestore(&dev->lock, flags);
|
||||
|
||||
if (retval) { /* TODO */
|
||||
printf("target device_add failed, error %d\n", retval);
|
||||
return retval;
|
||||
}
|
||||
|
||||
retval = driver->bind(&dev->gadget);
|
||||
if (retval) {
|
||||
DEBUG_SETUP("%s: bind to driver --> error %d\n",
|
||||
dev->gadget.name, retval);
|
||||
dev->driver = 0;
|
||||
return retval;
|
||||
}
|
||||
|
||||
enable_irq(IRQ_OTG);
|
||||
|
||||
DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
|
||||
udc_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Unregister entry point for the peripheral controller driver.
|
||||
*/
|
||||
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
|
||||
{
|
||||
struct s3c_udc *dev = the_controller;
|
||||
unsigned long flags;
|
||||
|
||||
if (!dev)
|
||||
return -ENODEV;
|
||||
if (!driver || driver != dev->driver)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev->lock, flags);
|
||||
dev->driver = 0;
|
||||
stop_activity(dev, driver);
|
||||
spin_unlock_irqrestore(&dev->lock, flags);
|
||||
|
||||
driver->unbind(&dev->gadget);
|
||||
|
||||
disable_irq(IRQ_OTG);
|
||||
|
||||
udc_disable(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* done - retire a request; caller blocked irqs
|
||||
*/
|
||||
static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
|
||||
{
|
||||
unsigned int stopped = ep->stopped;
|
||||
|
||||
DEBUG("%s: %s %p, req = %p, stopped = %d\n",
|
||||
__func__, ep->ep.name, ep, &req->req, stopped);
|
||||
|
||||
list_del_init(&req->queue);
|
||||
|
||||
if (likely(req->req.status == -EINPROGRESS))
|
||||
req->req.status = status;
|
||||
else
|
||||
status = req->req.status;
|
||||
|
||||
if (status && status != -ESHUTDOWN) {
|
||||
DEBUG("complete %s req %p stat %d len %u/%u\n",
|
||||
ep->ep.name, &req->req, status,
|
||||
req->req.actual, req->req.length);
|
||||
}
|
||||
|
||||
/* don't modify queue heads during completion callback */
|
||||
ep->stopped = 1;
|
||||
|
||||
#ifdef DEBUG_S3C_UDC
|
||||
printf("calling complete callback\n");
|
||||
{
|
||||
int i, len = req->req.length;
|
||||
|
||||
printf("pkt[%d] = ", req->req.length);
|
||||
if (len > 64)
|
||||
len = 64;
|
||||
for (i = 0; i < len; i++) {
|
||||
printf("%02x", ((u8 *)req->req.buf)[i]);
|
||||
if ((i & 7) == 7)
|
||||
printf(" ");
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
spin_unlock(&ep->dev->lock);
|
||||
req->req.complete(&ep->ep, &req->req);
|
||||
spin_lock(&ep->dev->lock);
|
||||
|
||||
DEBUG("callback completed\n");
|
||||
|
||||
ep->stopped = stopped;
|
||||
}
|
||||
|
||||
/*
|
||||
* nuke - dequeue ALL requests
|
||||
*/
|
||||
static void nuke(struct s3c_ep *ep, int status)
|
||||
{
|
||||
struct s3c_request *req;
|
||||
|
||||
DEBUG("%s: %s %p\n", __func__, ep->ep.name, ep);
|
||||
|
||||
/* called with irqs blocked */
|
||||
while (!list_empty(&ep->queue)) {
|
||||
req = list_entry(ep->queue.next, struct s3c_request, queue);
|
||||
done(ep, req, status);
|
||||
}
|
||||
}
|
||||
|
||||
static void stop_activity(struct s3c_udc *dev,
|
||||
struct usb_gadget_driver *driver)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* don't disconnect drivers more than once */
|
||||
if (dev->gadget.speed == USB_SPEED_UNKNOWN)
|
||||
driver = 0;
|
||||
dev->gadget.speed = USB_SPEED_UNKNOWN;
|
||||
|
||||
/* prevent new request submissions, kill any outstanding requests */
|
||||
for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
|
||||
struct s3c_ep *ep = &dev->ep[i];
|
||||
ep->stopped = 1;
|
||||
nuke(ep, -ESHUTDOWN);
|
||||
}
|
||||
|
||||
/* report disconnect; the driver is already quiesced */
|
||||
if (driver) {
|
||||
spin_unlock(&dev->lock);
|
||||
driver->disconnect(&dev->gadget);
|
||||
spin_lock(&dev->lock);
|
||||
}
|
||||
|
||||
/* re-init driver-visible data structures */
|
||||
udc_reinit(dev);
|
||||
}
|
||||
|
||||
static void reconfig_usbd(void)
|
||||
{
|
||||
/* 2. Soft-reset OTG Core and then unreset again. */
|
||||
int i;
|
||||
unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl);
|
||||
|
||||
DEBUG(2, "Reseting OTG controller\n");
|
||||
|
||||
writel(0<<15 /* PHY Low Power Clock sel*/
|
||||
|1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
|
||||
|0x5<<10 /* Turnaround time*/
|
||||
|0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
|
||||
/* 1:SRP enable] H1= 1,1*/
|
||||
|0<<7 /* Ulpi DDR sel*/
|
||||
|0<<6 /* 0: high speed utmi+, 1: full speed serial*/
|
||||
|0<<4 /* 0: utmi+, 1:ulpi*/
|
||||
|1<<3 /* phy i/f 0:8bit, 1:16bit*/
|
||||
|0x7<<0, /* HS/FS Timeout**/
|
||||
®->gusbcfg);
|
||||
|
||||
/* 3. Put the OTG device core in the disconnected state.*/
|
||||
uTemp = readl(®->dctl);
|
||||
uTemp |= SOFT_DISCONNECT;
|
||||
writel(uTemp, ®->dctl);
|
||||
|
||||
udelay(20);
|
||||
|
||||
/* 4. Make the OTG device core exit from the disconnected state.*/
|
||||
uTemp = readl(®->dctl);
|
||||
uTemp = uTemp & ~SOFT_DISCONNECT;
|
||||
writel(uTemp, ®->dctl);
|
||||
|
||||
/* 5. Configure OTG Core to initial settings of device mode.*/
|
||||
/* [][1: full speed(30Mhz) 0:high speed]*/
|
||||
writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, ®->dcfg);
|
||||
|
||||
mdelay(1);
|
||||
|
||||
/* 6. Unmask the core interrupts*/
|
||||
writel(GINTMSK_INIT, ®->gintmsk);
|
||||
|
||||
/* 7. Set NAK bit of EP0, EP1, EP2*/
|
||||
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl);
|
||||
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl);
|
||||
|
||||
for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
|
||||
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl);
|
||||
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl);
|
||||
}
|
||||
|
||||
/* 8. Unmask EPO interrupts*/
|
||||
writel(((1 << EP0_CON) << DAINT_OUT_BIT)
|
||||
| (1 << EP0_CON), ®->daintmsk);
|
||||
|
||||
/* 9. Unmask device OUT EP common interrupts*/
|
||||
writel(DOEPMSK_INIT, ®->doepmsk);
|
||||
|
||||
/* 10. Unmask device IN EP common interrupts*/
|
||||
writel(DIEPMSK_INIT, ®->diepmsk);
|
||||
|
||||
/* 11. Set Rx FIFO Size (in 32-bit words) */
|
||||
writel(RX_FIFO_SIZE >> 2, ®->grxfsiz);
|
||||
|
||||
/* 12. Set Non Periodic Tx FIFO Size */
|
||||
writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
|
||||
®->gnptxfsiz);
|
||||
|
||||
for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
|
||||
writel((PTX_FIFO_SIZE >> 2) << 16 |
|
||||
((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
|
||||
PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
|
||||
®->dieptxf[i-1]);
|
||||
|
||||
/* Flush the RX FIFO */
|
||||
writel(RX_FIFO_FLUSH, ®->grstctl);
|
||||
while (readl(®->grstctl) & RX_FIFO_FLUSH)
|
||||
DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
|
||||
|
||||
/* Flush all the Tx FIFO's */
|
||||
writel(TX_FIFO_FLUSH_ALL, ®->grstctl);
|
||||
writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl);
|
||||
while (readl(®->grstctl) & TX_FIFO_FLUSH)
|
||||
DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
|
||||
|
||||
/* 13. Clear NAK bit of EP0, EP1, EP2*/
|
||||
/* For Slave mode*/
|
||||
/* EP0: Control OUT */
|
||||
writel(DEPCTL_EPDIS | DEPCTL_CNAK,
|
||||
®->out_endp[EP0_CON].doepctl);
|
||||
|
||||
/* 14. Initialize OTG Link Core.*/
|
||||
writel(GAHBCFG_INIT, ®->gahbcfg);
|
||||
}
|
||||
|
||||
static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
|
||||
{
|
||||
unsigned int ep_ctrl;
|
||||
int i;
|
||||
|
||||
if (speed == USB_SPEED_HIGH) {
|
||||
ep0_fifo_size = 64;
|
||||
ep_fifo_size = 512;
|
||||
ep_fifo_size2 = 1024;
|
||||
dev->gadget.speed = USB_SPEED_HIGH;
|
||||
} else {
|
||||
ep0_fifo_size = 64;
|
||||
ep_fifo_size = 64;
|
||||
ep_fifo_size2 = 64;
|
||||
dev->gadget.speed = USB_SPEED_FULL;
|
||||
}
|
||||
|
||||
dev->ep[0].ep.maxpacket = ep0_fifo_size;
|
||||
for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
|
||||
dev->ep[i].ep.maxpacket = ep_fifo_size;
|
||||
|
||||
/* EP0 - Control IN (64 bytes)*/
|
||||
ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
|
||||
writel(ep_ctrl|(0<<0), ®->in_endp[EP0_CON].diepctl);
|
||||
|
||||
/* EP0 - Control OUT (64 bytes)*/
|
||||
ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
|
||||
writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl);
|
||||
}
|
||||
|
||||
static int s3c_ep_enable(struct usb_ep *_ep,
|
||||
const struct usb_endpoint_descriptor *desc)
|
||||
{
|
||||
struct s3c_ep *ep;
|
||||
struct s3c_udc *dev;
|
||||
unsigned long flags;
|
||||
|
||||
DEBUG("%s: %p\n", __func__, _ep);
|
||||
|
||||
ep = container_of(_ep, struct s3c_ep, ep);
|
||||
if (!_ep || !desc || ep->desc || _ep->name == ep0name
|
||||
|| desc->bDescriptorType != USB_DT_ENDPOINT
|
||||
|| ep->bEndpointAddress != desc->bEndpointAddress
|
||||
|| ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
|
||||
|
||||
DEBUG("%s: bad ep or descriptor\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* xfer types must match, except that interrupt ~= bulk */
|
||||
if (ep->bmAttributes != desc->bmAttributes
|
||||
&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
|
||||
&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
|
||||
|
||||
DEBUG("%s: %s type mismatch\n", __func__, _ep->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* hardware _could_ do smaller, but driver doesn't */
|
||||
if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
|
||||
&& le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
|
||||
|| !desc->wMaxPacketSize) {
|
||||
|
||||
DEBUG("%s: bad %s maxpacket\n", __func__, _ep->name);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
dev = ep->dev;
|
||||
if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
|
||||
|
||||
DEBUG("%s: bogus device state\n", __func__);
|
||||
return -ESHUTDOWN;
|
||||
}
|
||||
|
||||
ep->stopped = 0;
|
||||
ep->desc = desc;
|
||||
ep->pio_irqs = 0;
|
||||
ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
|
||||
|
||||
/* Reset halt state */
|
||||
s3c_udc_set_nak(ep);
|
||||
s3c_udc_set_halt(_ep, 0);
|
||||
|
||||
spin_lock_irqsave(&ep->dev->lock, flags);
|
||||
s3c_udc_ep_activate(ep);
|
||||
spin_unlock_irqrestore(&ep->dev->lock, flags);
|
||||
|
||||
DEBUG("%s: enabled %s, stopped = %d, maxpacket = %d\n",
|
||||
__func__, _ep->name, ep->stopped, ep->ep.maxpacket);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable EP
|
||||
*/
|
||||
static int s3c_ep_disable(struct usb_ep *_ep)
|
||||
{
|
||||
struct s3c_ep *ep;
|
||||
unsigned long flags;
|
||||
|
||||
DEBUG("%s: %p\n", __func__, _ep);
|
||||
|
||||
ep = container_of(_ep, struct s3c_ep, ep);
|
||||
if (!_ep || !ep->desc) {
|
||||
DEBUG("%s: %s not enabled\n", __func__,
|
||||
_ep ? ep->ep.name : NULL);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&ep->dev->lock, flags);
|
||||
|
||||
/* Nuke all pending requests */
|
||||
nuke(ep, -ESHUTDOWN);
|
||||
|
||||
ep->desc = 0;
|
||||
ep->stopped = 1;
|
||||
|
||||
spin_unlock_irqrestore(&ep->dev->lock, flags);
|
||||
|
||||
DEBUG("%s: disabled %s\n", __func__, _ep->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
|
||||
gfp_t gfp_flags)
|
||||
{
|
||||
struct s3c_request *req;
|
||||
|
||||
DEBUG("%s: %s %p\n", __func__, ep->name, ep);
|
||||
|
||||
req = kmalloc(sizeof *req, gfp_flags);
|
||||
if (!req)
|
||||
return 0;
|
||||
|
||||
memset(req, 0, sizeof *req);
|
||||
INIT_LIST_HEAD(&req->queue);
|
||||
|
||||
return &req->req;
|
||||
}
|
||||
|
||||
static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
|
||||
{
|
||||
struct s3c_request *req;
|
||||
|
||||
DEBUG("%s: %p\n", __func__, ep);
|
||||
|
||||
req = container_of(_req, struct s3c_request, req);
|
||||
WARN_ON(!list_empty(&req->queue));
|
||||
kfree(req);
|
||||
}
|
||||
|
||||
/* dequeue JUST ONE request */
|
||||
static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
|
||||
{
|
||||
struct s3c_ep *ep;
|
||||
struct s3c_request *req;
|
||||
unsigned long flags;
|
||||
|
||||
DEBUG("%s: %p\n", __func__, _ep);
|
||||
|
||||
ep = container_of(_ep, struct s3c_ep, ep);
|
||||
if (!_ep || ep->ep.name == ep0name)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&ep->dev->lock, flags);
|
||||
|
||||
/* make sure it's actually queued on this endpoint */
|
||||
list_for_each_entry(req, &ep->queue, queue) {
|
||||
if (&req->req == _req)
|
||||
break;
|
||||
}
|
||||
if (&req->req != _req) {
|
||||
spin_unlock_irqrestore(&ep->dev->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
done(ep, req, -ECONNRESET);
|
||||
|
||||
spin_unlock_irqrestore(&ep->dev->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return bytes in EP FIFO
|
||||
*/
|
||||
static int s3c_fifo_status(struct usb_ep *_ep)
|
||||
{
|
||||
int count = 0;
|
||||
struct s3c_ep *ep;
|
||||
|
||||
ep = container_of(_ep, struct s3c_ep, ep);
|
||||
if (!_ep) {
|
||||
DEBUG("%s: bad ep\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
DEBUG("%s: %d\n", __func__, ep_index(ep));
|
||||
|
||||
/* LPD can't report unclaimed bytes from IN fifos */
|
||||
if (ep_is_in(ep))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush EP FIFO
|
||||
*/
|
||||
static void s3c_fifo_flush(struct usb_ep *_ep)
|
||||
{
|
||||
struct s3c_ep *ep;
|
||||
|
||||
ep = container_of(_ep, struct s3c_ep, ep);
|
||||
if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
|
||||
DEBUG("%s: bad ep\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
DEBUG("%s: %d\n", __func__, ep_index(ep));
|
||||
}
|
||||
|
||||
static const struct usb_gadget_ops s3c_udc_ops = {
|
||||
/* current versions must always be self-powered */
|
||||
};
|
||||
|
||||
static struct s3c_udc memory = {
|
||||
.usb_address = 0,
|
||||
.gadget = {
|
||||
.ops = &s3c_udc_ops,
|
||||
.ep0 = &memory.ep[0].ep,
|
||||
.name = driver_name,
|
||||
},
|
||||
|
||||
/* control endpoint */
|
||||
.ep[0] = {
|
||||
.ep = {
|
||||
.name = ep0name,
|
||||
.ops = &s3c_ep_ops,
|
||||
.maxpacket = EP0_FIFO_SIZE,
|
||||
},
|
||||
.dev = &memory,
|
||||
|
||||
.bEndpointAddress = 0,
|
||||
.bmAttributes = 0,
|
||||
|
||||
.ep_type = ep_control,
|
||||
},
|
||||
|
||||
/* first group of endpoints */
|
||||
.ep[1] = {
|
||||
.ep = {
|
||||
.name = "ep1in-bulk",
|
||||
.ops = &s3c_ep_ops,
|
||||
.maxpacket = EP_FIFO_SIZE,
|
||||
},
|
||||
.dev = &memory,
|
||||
|
||||
.bEndpointAddress = USB_DIR_IN | 1,
|
||||
.bmAttributes = USB_ENDPOINT_XFER_BULK,
|
||||
|
||||
.ep_type = ep_bulk_out,
|
||||
.fifo_num = 1,
|
||||
},
|
||||
|
||||
.ep[2] = {
|
||||
.ep = {
|
||||
.name = "ep2out-bulk",
|
||||
.ops = &s3c_ep_ops,
|
||||
.maxpacket = EP_FIFO_SIZE,
|
||||
},
|
||||
.dev = &memory,
|
||||
|
||||
.bEndpointAddress = USB_DIR_OUT | 2,
|
||||
.bmAttributes = USB_ENDPOINT_XFER_BULK,
|
||||
|
||||
.ep_type = ep_bulk_in,
|
||||
.fifo_num = 2,
|
||||
},
|
||||
|
||||
.ep[3] = {
|
||||
.ep = {
|
||||
.name = "ep3in-int",
|
||||
.ops = &s3c_ep_ops,
|
||||
.maxpacket = EP_FIFO_SIZE,
|
||||
},
|
||||
.dev = &memory,
|
||||
|
||||
.bEndpointAddress = USB_DIR_IN | 3,
|
||||
.bmAttributes = USB_ENDPOINT_XFER_INT,
|
||||
|
||||
.ep_type = ep_interrupt,
|
||||
.fifo_num = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* probe - binds to the platform device
|
||||
*/
|
||||
|
||||
int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
|
||||
{
|
||||
struct s3c_udc *dev = &memory;
|
||||
int retval = 0, i;
|
||||
|
||||
DEBUG("%s: %p\n", __func__, pdata);
|
||||
|
||||
dev->pdata = pdata;
|
||||
|
||||
phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
|
||||
reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
|
||||
usb_phy_ctrl = pdata->usb_phy_ctrl;
|
||||
|
||||
/* regs_otg = (void *)pdata->regs_otg; */
|
||||
|
||||
dev->gadget.is_dualspeed = 1; /* Hack only*/
|
||||
dev->gadget.is_otg = 0;
|
||||
dev->gadget.is_a_peripheral = 0;
|
||||
dev->gadget.b_hnp_enable = 0;
|
||||
dev->gadget.a_hnp_support = 0;
|
||||
dev->gadget.a_alt_hnp_support = 0;
|
||||
|
||||
the_controller = dev;
|
||||
|
||||
for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
|
||||
dev->dma_buf[i] = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
|
||||
dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
|
||||
invalidate_dcache_range((unsigned long) dev->dma_buf[i],
|
||||
(unsigned long) (dev->dma_buf[i]
|
||||
+ DMA_BUFFER_SIZE));
|
||||
}
|
||||
usb_ctrl = dev->dma_buf[0];
|
||||
usb_ctrl_dma_addr = dev->dma_addr[0];
|
||||
|
||||
udc_reinit(dev);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int usb_gadget_handle_interrupts()
|
||||
{
|
||||
u32 intr_status = readl(®->gintsts);
|
||||
u32 gintmsk = readl(®->gintmsk);
|
||||
|
||||
if (intr_status & gintmsk)
|
||||
return s3c_udc_irq(1, (void *)the_controller);
|
||||
return 0;
|
||||
}
|
||||
1444
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
Normal file
1444
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
Normal file
File diff suppressed because it is too large
Load Diff
62
include/usb/lin_gadget_compat.h
Normal file
62
include/usb/lin_gadget_compat.h
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2011 Samsung Electronics
|
||||
* Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This is a Linux kernel compatibility layer for USB Gadget
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __LIN_COMPAT_H__
|
||||
#define __LIN_COMPAT_H__
|
||||
|
||||
/* common */
|
||||
#define spin_lock_init(...)
|
||||
#define spin_lock(...)
|
||||
#define spin_lock_irqsave(lock, flags) do {flags = 1; } while (0)
|
||||
#define spin_unlock(...)
|
||||
#define spin_unlock_irqrestore(lock, flags) do {flags = 0; } while (0)
|
||||
#define disable_irq(...)
|
||||
#define enable_irq(...)
|
||||
|
||||
#define mutex_init(...)
|
||||
#define mutex_lock(...)
|
||||
#define mutex_unlock(...)
|
||||
|
||||
#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
|
||||
, __FILE__, __LINE__); }
|
||||
|
||||
#define KERN_WARNING
|
||||
#define KERN_ERR
|
||||
#define KERN_NOTICE
|
||||
#define KERN_DEBUG
|
||||
|
||||
#define GFP_KERNEL 0
|
||||
|
||||
#define IRQ_HANDLED 1
|
||||
|
||||
#define ENOTSUPP 524 /* Operation is not supported */
|
||||
|
||||
#define kmalloc(size, type) memalign(CONFIG_SYS_CACHELINE_SIZE, size)
|
||||
#define kfree(addr) free(addr)
|
||||
#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
|
||||
|
||||
#define __iomem
|
||||
#define min_t min
|
||||
#define dma_cache_maint(addr, size, mode) cache_flush()
|
||||
void cache_flush(void);
|
||||
|
||||
#endif /* __LIN_COMPAT_H__ */
|
||||
175
include/usb/s3c_udc.h
Normal file
175
include/usb/s3c_udc.h
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* drivers/usb/gadget/s3c_udc.h
|
||||
* Samsung S3C on-chip full/high speed USB device controllers
|
||||
* Copyright (C) 2005 for Samsung Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __S3C_USB_GADGET
|
||||
#define __S3C_USB_GADGET
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <linux/usb/ch9.h>
|
||||
#include <linux/usb/gadget.h>
|
||||
#include <linux/list.h>
|
||||
#include <usb/lin_gadget_compat.h>
|
||||
|
||||
#define PHY0_SLEEP (1 << 5)
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* DMA bounce buffer size, 16K is enough even for mass storage */
|
||||
#define DMA_BUFFER_SIZE (4096*4)
|
||||
|
||||
#define EP0_FIFO_SIZE 64
|
||||
#define EP_FIFO_SIZE 512
|
||||
#define EP_FIFO_SIZE2 1024
|
||||
/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
|
||||
#define S3C_MAX_ENDPOINTS 4
|
||||
#define S3C_MAX_HW_ENDPOINTS 16
|
||||
|
||||
#define WAIT_FOR_SETUP 0
|
||||
#define DATA_STATE_XMIT 1
|
||||
#define DATA_STATE_NEED_ZLP 2
|
||||
#define WAIT_FOR_OUT_STATUS 3
|
||||
#define DATA_STATE_RECV 4
|
||||
#define WAIT_FOR_COMPLETE 5
|
||||
#define WAIT_FOR_OUT_COMPLETE 6
|
||||
#define WAIT_FOR_IN_COMPLETE 7
|
||||
#define WAIT_FOR_NULL_COMPLETE 8
|
||||
|
||||
#define TEST_J_SEL 0x1
|
||||
#define TEST_K_SEL 0x2
|
||||
#define TEST_SE0_NAK_SEL 0x3
|
||||
#define TEST_PACKET_SEL 0x4
|
||||
#define TEST_FORCE_ENABLE_SEL 0x5
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* IO
|
||||
*/
|
||||
|
||||
enum ep_type {
|
||||
ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
|
||||
};
|
||||
|
||||
struct s3c_ep {
|
||||
struct usb_ep ep;
|
||||
struct s3c_udc *dev;
|
||||
|
||||
const struct usb_endpoint_descriptor *desc;
|
||||
struct list_head queue;
|
||||
unsigned long pio_irqs;
|
||||
int len;
|
||||
void *dma_buf;
|
||||
|
||||
u8 stopped;
|
||||
u8 bEndpointAddress;
|
||||
u8 bmAttributes;
|
||||
|
||||
enum ep_type ep_type;
|
||||
int fifo_num;
|
||||
};
|
||||
|
||||
struct s3c_request {
|
||||
struct usb_request req;
|
||||
struct list_head queue;
|
||||
};
|
||||
|
||||
struct s3c_udc {
|
||||
struct usb_gadget gadget;
|
||||
struct usb_gadget_driver *driver;
|
||||
|
||||
struct s3c_plat_otg_data *pdata;
|
||||
|
||||
void *dma_buf[S3C_MAX_ENDPOINTS+1];
|
||||
dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1];
|
||||
|
||||
int ep0state;
|
||||
struct s3c_ep ep[S3C_MAX_ENDPOINTS];
|
||||
|
||||
unsigned char usb_address;
|
||||
|
||||
unsigned req_pending:1, req_std:1, req_config:1;
|
||||
};
|
||||
|
||||
extern struct s3c_udc *the_controller;
|
||||
|
||||
#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
|
||||
#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
|
||||
#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* #define DEBUG_UDC */
|
||||
#ifdef DEBUG_UDC
|
||||
#define DBG(stuff...) printf("udc: " stuff)
|
||||
#else
|
||||
#define DBG(stuff...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC_SETUP
|
||||
#define DEBUG_SETUP(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG_SETUP(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC_EP0
|
||||
#define DEBUG_EP0(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG_EP0(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC
|
||||
#define DEBUG(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC_ISR
|
||||
#define DEBUG_ISR(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG_ISR(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC_OUT_EP
|
||||
#define DEBUG_OUT_EP(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG_OUT_EP(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_S3C_UDC_IN_EP
|
||||
#define DEBUG_IN_EP(fmt, args...) printk(fmt, ##args)
|
||||
#else
|
||||
#define DEBUG_IN_EP(fmt, args...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#define ERR(stuff...) printf("ERR udc: " stuff)
|
||||
#define WARN(stuff...) printf("WARNING udc: " stuff)
|
||||
#define INFO(stuff...) printf("INFO udc: " stuff)
|
||||
|
||||
extern void otg_phy_init(struct s3c_udc *dev);
|
||||
extern void otg_phy_off(struct s3c_udc *dev);
|
||||
|
||||
extern void s3c_udc_ep_set_stall(struct s3c_ep *ep);
|
||||
extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
|
||||
|
||||
struct s3c_plat_otg_data {
|
||||
int (*phy_control)(int on);
|
||||
unsigned int regs_phy;
|
||||
unsigned int regs_otg;
|
||||
unsigned int usb_phy_ctrl;
|
||||
unsigned int usb_flags;
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user