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MIPS: Split I & D cache line size config

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Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton
2016-05-27 14:28:05 +01:00
committed by Daniel Schwierzeck
parent ace3be4f15
commit 372286217f
12 changed files with 54 additions and 29 deletions
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24
arch/mips/lib/cache.c
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@@ -9,23 +9,13 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
static inline unsigned long icache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
static inline unsigned long dcache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
#else /* !CONFIG_SYS_CACHELINE_SIZE */
static inline unsigned long icache_line_size(void)
{
unsigned long conf1, il;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_ICACHE_LINE_SIZE;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_DCACHE_LINE_SIZE;
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
return 2 << dl;
}
#endif /* !CONFIG_SYS_CACHELINE_SIZE */
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();