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Add out4.ru O4-iMX-NANO board

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Board designed for quick prototyping and has one microSD port,
2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO,
UART interfaces, and 2 RGB LEDs.

Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Oleh Kravchenko
2021-05-15 00:18:31 +03:00
committed by Stefano Babic
parent e2017ef6ed
commit 3675ac081a
12 changed files with 819 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
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@@ -819,6 +819,9 @@ dtb-$(CONFIG_ARCH_MX6) += \
imx6-apalis.dtb \
imx6-colibri.dtb
dtb-$(CONFIG_O4_IMX_NANO) += \
o4-imx-nano.dtb
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
imx7-cm.dtb \

241
arch/arm/dts/o4-imx-nano.dts Normal file
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@@ -0,0 +1,241 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "o4-imx6ull-nano.dtsi"
/ {
model = "O4-iMX-NANO";
compatible = "out4,o4-imx-nano",
"out4,o4-imx6ull-nano",
"fsl,imx6ull";
aliases {
mmc1 = &usdhc1;
};
chosen {
stdout-path = &uart1;
};
leds {
compatible = "gpio-leds";
led@0 {
color = <LED_COLOR_ID_RED>;
gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>;
reg = <0>;
};
led@1 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>;
reg = <1>;
};
led@2 {
gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_BLUE>;
reg = <2>;
};
led@3 {
color = <LED_COLOR_ID_RED>;
gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
reg = <3>;
};
led@4 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>;
reg = <4>;
};
led@5 {
color = <LED_COLOR_ID_BLUE>;
gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>;
reg = <5>;
};
};
usbotg1_vbus: reg_usbotg1_vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb0";
};
usbotg2_vbus: reg_usbotg2_vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1";
};
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
>;
};
pinctrl_mdio: mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&usdhc1 {
bus-width = <4>;
no-1-8-v;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default";
status = "okay";
wakeup-source;
};
&fec1 {
phy-handle = <&phy0>;
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-names = "default";
status = "okay";
};
&fec2 {
phy-handle = <&phy1>;
phy-mode = "rmii";
phy-reset-duration = <250>;
phy-reset-post-delay = <100>;
phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_phy0_irq>;
pinctrl-names = "default";
reg = <0>;
};
phy1: ethernet-phy@1 {
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
interrupt-parent = <&gpio5>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_phy1_irq>;
pinctrl-names = "default";
reg = <1>;
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
vbus-supply = <&usbotg1_vbus>;
};
&usbotg2 {
dr_mode = "host";
status = "okay";
vbus-supply = <&usbotg2_vbus>;
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pcf8574a: gpio@38 {
compatible = "nxp,pcf8574a";
#gpio-cells = <2>;
gpio-controller;
reg = <0x38>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&uart2 {
linux,rs485-enabled-at-boot-time;
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
status = "okay";
uart-has-rtscts;
};

87
arch/arm/dts/o4-imx6ull-nano.dtsi Normal file
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@@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
/dts-v1/;
#include "imx6ull.dtsi"
/ {
model = "O4-iMX6ULL-NANO";
compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull";
aliases {
mmc0 = &usdhc2;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
pinctrl_phy0_irq: phy0grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79
>;
};
pinctrl_phy1_irq: phy1grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
>;
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
bus-width = <8>;
status = "okay";
};

13
arch/arm/mach-imx/mx6/Kconfig
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@@ -619,6 +619,18 @@ config TARGET_BRPPT2
Support
B&R BRPPT2 platform
based on Freescale's iMX6 SoC
config TARGET_O4_IMX6ULL_NANO
bool "O4-iMX6ULL-NANO"
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_THERMAL
imply CMD_DM
help
Support for www.out4.ru O4-iMX6UL-NANO platform
based on Freescale's i.MX6UL/i.MX6ULL SoC.
endchoice
config SYS_SOC
@@ -668,5 +680,6 @@ source "board/udoo/neo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/BuR/brppt2/Kconfig"
source "board/out4/o4-imx6ull-nano/Kconfig"
endif