sunxi: display: Move DDC PLL setup to HDMI init
Move PLL initialization code to single place so we won't call it every time we query for EDID data. Signed-off-by: Priit Laes <priit.laes@paf.com>
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@ -113,6 +113,13 @@ static int sunxi_hdmi_hpd_detect(int hpd_delay)
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writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
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writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
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/* Enable PLLs for eventual DDC */
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writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
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&hdmi->pad_ctrl1);
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writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
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&hdmi->pll_ctrl);
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writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
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while (timer_get_us() < tmo) {
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if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
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return 1;
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@ -215,13 +222,6 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int i, r, ext_blocks = 0;
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/* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
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writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
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&hdmi->pad_ctrl1);
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writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
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&hdmi->pll_ctrl);
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writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
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/* Reset i2c controller */
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setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
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writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
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