ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3
This patch fixes the write-protect control of CPG. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
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@ -27,7 +27,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE615090C
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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void s_init(void)
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@ -39,8 +39,8 @@ void s_init(void)
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xFFFFFFFF, CPGWPR);
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}
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define GSX_MSTP112 BIT(12) /* 3DG */
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@ -28,7 +28,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE615090C
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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void s_init(void)
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@ -40,8 +40,8 @@ void s_init(void)
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xFFFFFFFF, CPGWPR);
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}
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define GSX_MSTP112 BIT(12) /* 3DG */
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@ -27,7 +27,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE615090C
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#define CPGWPR 0xE6150900
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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void s_init(void)
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@ -39,8 +39,8 @@ void s_init(void)
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xA5A50000, CPGWPCR);
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writel(0xFFFFFFFF, CPGWPR);
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}
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define GSX_MSTP112 BIT(12) /* 3DG */
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