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Reorder CHANGELOG

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This commit is contained in:
Stefan Roese 2006-03-31 15:18:37 +02:00
parent 62534beb2f
commit 3511853943
1 changed files with 18 additions and 18 deletions
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36
CHANGELOG
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@ -2,6 +2,24 @@
Changes since U-Boot 1.1.4:
======================================================================
* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
* Enable Quad UART om MCC200 board.
* Cleanup MCC200 board configuration; omit non-existent stuff.
@ -33,24 +51,6 @@ Changes since U-Boot 1.1.4:
* Add support for Lite5200B board.
Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
timer and cpu_reset code from cpu/$(CPU) into the new
cpu/$(CPU)/$(SOC) directories