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armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

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Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Michael Walle <michael@walle.cc> [for kontron-sl28]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Yangbo Lu 2021-06-03 10:51:19 +08:00 committed by Priyanka Jain
parent b1d59867e5
commit 34f39ce882
17 changed files with 15 additions and 84 deletions
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3
include/configs/T208xQDS.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -618,7 +618,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*

3
include/configs/T208xRDB.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -574,7 +574,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*

3
include/configs/T4240RDB.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -585,7 +585,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

5
include/configs/kontron_sl28.h
View File

@ -56,11 +56,6 @@
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* ethernet */
#define CONFIG_SYS_RX_ETH_BUFFER 8

7
include/configs/ls1012a2g5rdb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
* Copyright 2017, 2021 NXP
*/
#ifndef __LS1012A2G5RDB_H__
@ -13,11 +13,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI

7
include/configs/ls1012afrwy.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#ifndef __LS1012AFRWY_H__
@ -33,11 +33,6 @@
func(DHCP, dhcp, na)
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW

6
include/configs/ls1012aqds.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#ifndef __LS1012AQDS_H__
@ -93,11 +94,6 @@
DSPI_CTAR_DT(0))
#define CONFIG_SPI_FLASH_EON /* cs3 */
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW

8
include/configs/ls1012ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor, Inc.
*/
@ -38,12 +38,6 @@
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW

7
include/configs/ls1028a_common.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __L1028A_COMMON_H
@ -93,11 +93,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define OCRAM_NONSECURE_SIZE 0x00010000
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000

9
include/configs/ls1043a_common.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1043A_COMMON_H
@ -171,13 +171,6 @@
#endif
#endif
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
/* DSPI */
#ifndef SPL_NO_DSPI
#ifdef CONFIG_FSL_DSPI

9
include/configs/ls1046a_common.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1046A_COMMON_H
@ -165,13 +165,6 @@
CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN

3
include/configs/ls1088aqds.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2020 NXP
* Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_QDS_H
@ -361,7 +361,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_MEMAC
/* MMC */
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)

7
include/configs/ls1088ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2020 NXP
* Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_RDB_H
@ -507,11 +507,6 @@
#endif
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#ifndef SPL_NO_ENV
#define BOOT_TARGET_DEVICES(func) \

7
include/configs/ls2080aqds.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2019-2020 NXP
* Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
@ -318,11 +318,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC

7
include/configs/ls2080ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2019-2020 NXP
* Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
@ -300,11 +300,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \

7
include/configs/lx2160a_common.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*/
#ifndef __LX2_COMMON_H
@ -129,11 +129,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* SATA */
#ifdef CONFIG_SCSI

1
scripts/config_whitelist.txt
View File

@ -2307,7 +2307,6 @@ CONFIG_SYS_FSL_MAX_NUM_OF_SEC
CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
CONFIG_SYS_FSL_MC_BASE
CONFIG_SYS_FSL_MC_SIZE
CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
CONFIG_SYS_FSL_NI_BASE
CONFIG_SYS_FSL_NI_SIZE
CONFIG_SYS_FSL_NO_SERDES