MIPS: add support for Broadcom MIPS BCM6318 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Álvaro Fernández Rojas
Daniel Schwierzeck
parent
a80bf5e46e
commit
3483f28ebf
157
arch/mips/dts/brcm,bcm6318.dtsi
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157
arch/mips/dts/brcm,bcm6318.dtsi
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm6318-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/power-domain/bcm6318-power-domain.h>
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#include <dt-bindings/reset/bcm6318-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm6318";
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aliases {
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spi0 = &spi;
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};
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cpus {
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reg = <0x10000000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk: periph-clk {
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compatible = "brcm,bcm6345-clk";
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reg = <0x10000004 0x4>;
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#clock-cells = <1>;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_rst: reset-controller@10000010 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x10000010 0x4>;
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#reset-cells = <1>;
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};
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wdt: watchdog@10000068 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x10000068 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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pll_cntl: syscon@10000074 {
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compatible = "syscon";
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reg = <0x10000074 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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gpio1: gpio-controller@10000080 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000080 0x4>, <0x10000088 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <18>;
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status = "disabled";
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};
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gpio0: gpio-controller@10000084 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000084 0x4>, <0x1000008c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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uart0: serial@10000100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000100 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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leds: led-controller@10000200 {
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compatible = "brcm,bcm6328-leds";
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reg = <0x10000200 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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periph_pwr: power-controller@100008e8 {
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compatible = "brcm,bcm6328-power-domain";
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reg = <0x100008e8 0x4>;
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#power-domain-cells = <1>;
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};
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spi: spi@10003000 {
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compatible = "brcm,bcm6328-hsspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10003000 0x600>;
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clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
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clock-names = "hsspi", "pll";
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resets = <&periph_rst BCM6318_RST_SPI>;
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spi-max-frequency = <33333334>;
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num-cs = <3>;
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status = "disabled";
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};
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memory-controller@10004000 {
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compatible = "brcm,bcm6318-mc";
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reg = <0x10004000 0x38>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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@ -6,6 +6,7 @@ config SYS_MALLOC_F_LEN
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config SYS_SOC
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default "bcm3380" if SOC_BMIPS_BCM3380
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default "bcm6318" if SOC_BMIPS_BCM6318
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default "bcm6328" if SOC_BMIPS_BCM6328
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default "bcm6338" if SOC_BMIPS_BCM6338
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default "bcm6348" if SOC_BMIPS_BCM6348
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@ -27,6 +28,17 @@ config SOC_BMIPS_BCM3380
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help
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This supports BMIPS BCM3380 family.
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config SOC_BMIPS_BCM6318
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bool "BMIPS BCM6318 family"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select MIPS_TUNE_4KC
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select MIPS_L1_CACHE_SHIFT_4
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select SWAP_IO_SPACE
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select SYSRESET_SYSCON
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help
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This supports BMIPS BCM6318 family.
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config SOC_BMIPS_BCM6328
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bool "BMIPS BCM6328 family"
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select SUPPORTS_BIG_ENDIAN
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25
include/configs/bmips_bcm6318.h
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25
include/configs/bmips_bcm6318.h
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_BMIPS_BCM6318_H
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#define __CONFIG_BMIPS_BCM6318_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#endif /* __CONFIG_BMIPS_BCM6318_H */
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37
include/dt-bindings/clock/bcm6318-clock.h
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37
include/dt-bindings/clock/bcm6318-clock.h
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
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#define __DT_BINDINGS_CLOCK_BCM6318_H
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#define BCM6318_CLK_ADSL_ASB 0
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#define BCM6318_CLK_USB_ASB 1
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#define BCM6318_CLK_MIPS_ASB 2
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#define BCM6318_CLK_PCIE_ASB 3
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#define BCM6318_CLK_PHYMIPS_ASB 4
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#define BCM6318_CLK_ROBOSW_ASB 5
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#define BCM6318_CLK_SAR_ASB 6
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#define BCM6318_CLK_SDR_ASB 7
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#define BCM6318_CLK_SWREG_ASB 8
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#define BCM6318_CLK_PERIPH_ASB 9
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#define BCM6318_CLK_CPUBUS160 10
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#define BCM6318_CLK_ADSL 11
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#define BCM6318_CLK_SAR125 12
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#define BCM6318_CLK_MIPS 13
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#define BCM6318_CLK_PCIE 14
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#define BCM6318_CLK_ROBOSW250 16
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#define BCM6318_CLK_ROBOSW025 17
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#define BCM6318_CLK_SDR 19
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#define BCM6318_CLK_USB 20
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#define BCM6318_CLK_HSSPI 25
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#define BCM6318_CLK_PCIE25 27
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#define BCM6318_CLK_PHYMIPS 28
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#define BCM6318_CLK_AFE 29
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#define BCM6318_CLK_QPROC 30
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#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
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13
include/dt-bindings/power-domain/bcm6318-power-domain.h
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include/dt-bindings/power-domain/bcm6318-power-domain.h
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
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#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
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#define BCM6318_PWR_PCIE 0
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#define BCM6318_PWR_USB 1
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#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */
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26
include/dt-bindings/reset/bcm6318-reset.h
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include/dt-bindings/reset/bcm6318-reset.h
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM6318_H
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#define __DT_BINDINGS_RESET_BCM6318_H
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#define BCM6318_RST_SPI 0
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#define BCM6318_RST_EPHY 1
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#define BCM6318_RST_SAR 2
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#define BCM6318_RST_ENETSW 3
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#define BCM6318_RST_USBD 4
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#define BCM6318_RST_USBH 5
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#define BCM6318_RST_PCIE_CORE 6
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#define BCM6318_RST_PCIE 7
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#define BCM6318_RST_PCIE_EXT 8
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#define BCM6318_RST_PCIE_HARD 9
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#define BCM6318_RST_ADSL 10
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#define BCM6318_RST_PHYMIPS 11
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#define BCM6318_RST_HOSTMIPS 11
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#endif /* __DT_BINDINGS_RESET_BCM6318_H */
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