85xx: Added PCIe support for P1 P2 RDB
Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal
Kumar Gala
parent
0d3d68b25a
commit
33f3f34255
@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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117
board/freescale/p1_p2_rdb/pci.c
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117
board/freescale/p1_p2_rdb/pci.c
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@ -0,0 +1,117 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <asm/fsl_pci.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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void pci_init_board(void)
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{
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struct fsl_pci_info pci_info[2];
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = in_be32(&gur->devdisr);
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uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
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int num = 0;
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int first_free_busno = 0;
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int pcie_ep, pcie_configured;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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printf (" eTSEC2 is in sgmii mode.\n");
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#ifdef CONFIG_PCIE2
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = (host_agent == 2) || (host_agent == 4) ||
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(host_agent == 6) || (host_agent == 0);
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pcie_configured = (io_sel == 0xE);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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puts ("\n PCIE2 connected to Slot 1 as ");
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printf ("%s (base address %lx)",
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pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num],
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&pcie2_hose, first_free_busno);
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num++;
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} else {
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printf (" PCIE2: disabled\n");
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}
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#else
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set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
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(host_agent == 5);
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pcie_configured = (io_sel == 0xE);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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puts ("\n PCIE1 connected to Slot 2 as ");
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printf ("%s (base address %lx)",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num],
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&pcie1_hose, first_free_busno);
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num++;
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} else {
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printf (" PCIE1: disabled\n");
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}
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#else
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set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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}
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void ft_pci_board_setup(void *blob)
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{
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/* According to h/w manual, PCIE2 is at lower address(0x9000)
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* than PCIE1(0xa000).
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* Hence PCIE2 is made to occupy the pci1 position in dts to
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* keep the addresses sorted there.
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* Generally the case with all FSL SOCs.
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*/
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#ifdef CONFIG_PCIE2
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ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
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#endif
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
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#endif
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}
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@ -35,6 +35,12 @@
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
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#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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