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Revert "lpc32xx: cpu: add support for soft reset"

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This reverts commit 576007aec9.

The parameter passed to reset_cpu() no longer holds a meaning as all
call-sites now pass the value 0.  Thus, branching on it is essentially
dead code and will just confuse future readers.

Revert soft-reset support and just always perform a hard-reset for now.
This is a preparation for removal of the reset_cpu() parameter across
the entire tree in a later patch.

Fixes: 576007aec9 ("lpc32xx: cpu: add support for soft reset")
Cc: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Harald Seiler <hws@denx.de>
This commit is contained in:
Harald Seiler 2020-12-15 16:47:51 +01:00 committed by Tom Rini
parent 10b86ef9b3
commit 3394f398b5
1 changed files with 5 additions and 16 deletions
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21
arch/arm/mach-lpc32xx/cpu.c
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@ -22,23 +22,12 @@ void reset_cpu(ulong addr)
/* Enable watchdog clock */ /* Enable watchdog clock */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
/* To be compatible with the original U-Boot code: /* Reset pulse length is 13005 peripheral clock frames */
* addr: - 0: perform hard reset. writel(13000, &wdt->pulse);
* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
if (addr == 0) {
/* Reset pulse length is 13005 peripheral clock frames */
writel(13000, &wdt->pulse);
/* Force WDOG_RESET2 and RESOUT_N signal active */ /* Force WDOG_RESET2 and RESOUT_N signal active */
writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
| WDTIM_MCTRL_M_RES2, &wdt->mctrl); &wdt->mctrl);
} else {
/* Force match output active */
writel(0x01, &wdt->emr);
/* Internal reset on match output (no pulse on "RESOUT_N") */
writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
}
while (1) while (1)
/* NOP */; /* NOP */;