rockchip: rk3328: rock64 - fix gen3 SPL hang
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller <kurt@intricatesoftware.com> Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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@ -11,6 +11,22 @@
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};
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};
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};
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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&pinctrl {
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u-boot,dm-spl;
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};
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&sdmmc0m1_gpio {
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u-boot,dm-spl;
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};
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&pcfg_pull_up_4ma {
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u-boot,dm-spl;
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};
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&usb_host0_xhci {
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&usb_host0_xhci {
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vbus-supply = <&vcc_host_5v>;
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vbus-supply = <&vcc_host_5v>;
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status = "okay";
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status = "okay";
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@ -25,3 +41,8 @@
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/delete-property/ regulator-always-on;
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/delete-property/ regulator-always-on;
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/delete-property/ regulator-boot-on;
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/delete-property/ regulator-boot-on;
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};
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};
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/* Need this and all the pinctrl/gpio stuff above to set pinmux */
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&vcc_sd {
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u-boot,dm-spl;
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};
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@ -1,6 +1,7 @@
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CONFIG_ARM=y
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CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_ROCKCHIP_RK3328=y
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CONFIG_ROCKCHIP_RK3328=y
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CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_I2C_SUPPORT=y
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CONFIG_SPL_POWER_SUPPORT=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_BOOTZ=y
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@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_TPL_OF_CONTROL=y
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CONFIG_TPL_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
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CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_TPL_OF_PLATDATA=y
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CONFIG_TPL_OF_PLATDATA=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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@ -64,7 +67,9 @@ CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_SPL_DM_REGULATOR=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_SPL_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_PWM_ROCKCHIP=y
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