85xx: Add a 36-bit physical configuration for MPC8536DS
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
ecead84d56
commit
337f9fde2e
5
Makefile
5
Makefile
@ -2440,8 +2440,11 @@ vme8349_config: unconfig
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ATUM8548_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
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MPC8536DS_36BIT_config \
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MPC8536DS_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
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@$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale
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MPC8540ADS_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
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@ -27,6 +27,10 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_MPC8536DS_36BIT
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#define CONFIG_PHYS_64BIT 1
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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@ -77,6 +81,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x7fffffff
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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@ -87,7 +96,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
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#endif
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
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@ -96,6 +109,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
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/* DDR Setup */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_FSL_DDR2
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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@ -170,7 +184,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
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@ -178,7 +196,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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@ -199,7 +217,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
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#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
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#ifdef CONFIG_PHYS_64BIT
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#define PIXIS_BASE_PHYS 0xfffdf0000ull
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#else
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#define PIXIS_BASE_PHYS PIXIS_BASE
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#endif
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#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
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@ -254,8 +276,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
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CONFIG_SYS_NAND_BASE + 0x40000, \
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CONFIG_SYS_NAND_BASE + 0x80000, \
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@ -368,42 +394,78 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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*/
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#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
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#else
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#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
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#endif
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 1, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, direct to uli, tgtid 3, Base address 8000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
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#else
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
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#endif
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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#if defined(CONFIG_PCI)
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