From e6a727fffec7b2002edc9fdd467dea4ba0c6037a Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 27 Nov 2017 10:51:54 +0800 Subject: [PATCH 1/3] powerpc/T104xRDB: Fix endian access issue on EHCI intinalization This issue is exposed after commit 9000eddbae0d ("drivers/usb/ehci: Use platform-specific accessors"), the wrong endianness of EHCI controller programing will cause USB function down. Signed-off-by: Ran Wang Reviewed-by: York Sun --- include/configs/T104xRDB.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 2dbeffdd2a..9d82e1be78 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -634,6 +634,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_EHCI_DESC_BIG_ENDIAN #endif #endif From 0f2296bab1417faa5973e6d6690c8be0f83ecd08 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 27 Nov 2017 10:51:55 +0800 Subject: [PATCH 2/3] powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI intinalization This issue is exposed after commit 9000eddbae0d ("drivers/usb/ehci: Use platform-specific accessors"), the wrong endianness of EHCI controller programing will cause USB function down. Signed-off-by: Ran Wang Reviewed-by: York Sun --- include/configs/p1_p2_rdb_pc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b665b2c15..c51ca27502 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -782,6 +782,7 @@ #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_DESC_BIG_ENDIAN #endif #endif From 316f0d0f8f3cbeeefda043e69f3e4e6aa57f7f1d Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 5 Dec 2017 10:57:54 -0800 Subject: [PATCH 3/3] powerpc: mpc85xx: Fix static TLB table for SDRAM Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun --- board/Arcturus/ucp1020/tlb.c | 2 +- board/freescale/b4860qds/tlb.c | 2 +- board/freescale/bsc9131rdb/tlb.c | 2 +- board/freescale/bsc9132qds/tlb.c | 2 +- board/freescale/c29xpcie/tlb.c | 4 ++-- board/freescale/mpc8541cds/tlb.c | 2 +- board/freescale/mpc8548cds/tlb.c | 2 +- board/freescale/mpc8568mds/tlb.c | 2 +- board/freescale/p1010rdb/tlb.c | 2 +- board/freescale/p1022ds/tlb.c | 4 ++-- board/freescale/p1023rdb/tlb.c | 4 ++-- board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- board/freescale/p1_twr/tlb.c | 2 +- board/freescale/t102xqds/tlb.c | 4 ++-- board/freescale/t102xrdb/tlb.c | 4 ++-- board/freescale/t104xrdb/tlb.c | 4 ++-- board/freescale/t208xqds/tlb.c | 2 +- board/freescale/t208xrdb/tlb.c | 2 +- board/freescale/t4qds/tlb.c | 2 +- board/freescale/t4rdb/tlb.c | 2 +- board/gdsys/p1022/tlb.c | 2 +- board/sbc8548/tlb.c | 4 ++-- 22 files changed, 29 insertions(+), 29 deletions(-) diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c index fd7134f5cf..95d58af0e5 100644 --- a/board/Arcturus/ucp1020/tlb.c +++ b/board/Arcturus/ucp1020/tlb.c @@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = { (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, 0, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif /* RAMBOOT/SPL */ diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 7b55b860d0..88910d6cd1 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -147,7 +147,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 17, BOOKE_PAGESZ_2G, 1) #endif }; diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index c8ecf5de59..e5dab9ea30 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 07febc2b37..56199e5244 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -71,7 +71,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index c5abed0504..85d58c8cd4 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -67,11 +67,11 @@ struct fsl_e_tlb_entry tlb_table[] = { (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index fff3b4a7c2..6664f2755d 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf000_0000 64M LBC SDRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 6, BOOKE_PAGESZ_64M, 1), /* diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 363e043d06..571341ff68 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -48,7 +48,7 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 2, BOOKE_PAGESZ_64M, 1), /* diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index b5e2fec1f9..03d0fa1cd9 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf000_0000 64M LBC SDRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 4, BOOKE_PAGESZ_64M, 1), /* diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index af40f979d3..7d151f9e5f 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index e7ae2e25b2..69d5e449e0 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -75,12 +75,12 @@ struct fsl_e_tlb_entry tlb_table[] = { (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c index 8fd178e211..35a63fe026 100644 --- a/board/freescale/p1023rdb/tlb.c +++ b/board/freescale/p1023rdb/tlb.c @@ -86,12 +86,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_RAMBOOT SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_256M, 1), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 7cba411007..6324ebfa32 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c index 308335c974..0f365f9163 100644 --- a/board/freescale/p1_twr/tlb.c +++ b/board/freescale/p1_twr/tlb.c @@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_RAMBOOT /* *I*G - eSDHC boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c index 409e173999..0d27a998c5 100644 --- a/board/freescale/t102xqds/tlb.c +++ b/board/freescale/t102xqds/tlb.c @@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif /* entry 14 and 15 has been used hard coded, they will be disabled diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 8269b3d725..d77ce25784 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif /* entry 14 and 15 has been used hard coded, they will be disabled diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 7c0511e268..078947902f 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -120,11 +120,11 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif }; diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 8d602989b2..b0b3b4d48a 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -145,7 +145,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif }; diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 2ebea36a5c..2cae4d02b3 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -144,7 +144,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 1e4d096f5f..a6d8bb3603 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif }; diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 6a6b4b5cc1..648cfabeea 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -116,7 +116,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 18, BOOKE_PAGESZ_2G, 1) #endif }; diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c index aee86a4356..58b438fc14 100644 --- a/board/gdsys/p1022/tlb.c +++ b/board/gdsys/p1022/tlb.c @@ -65,7 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_RAMBOOT SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 6, BOOKE_PAGESZ_1G, 1), #endif #endif diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 2f7e4c5364..d2bf3049f1 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -66,7 +66,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 3, BOOKE_PAGESZ_64M, 1), /* @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 4, BOOKE_PAGESZ_64M, 1), #endif