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armv8/ls2085ardb: Enable NAND SPL support

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Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Scott Wood 2015-03-24 13:25:03 -07:00 committed by York Sun
parent 548cf52fd5
commit 32eda7cc94
6 changed files with 58 additions and 5 deletions
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1
arch/arm/Kconfig
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@ -726,6 +726,7 @@ config TARGET_LS2085ARDB
bool "Support ls2085ardb"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS2085ARDB platform.
The LS2085A Reference design board (RDB) is a high-performance

13
arch/arm/cpu/armv8/fsl-lsch3/README
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@ -133,3 +133,16 @@ The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>
With these two images in NAND device, the board can boot from NAND.
Another example for RDB boards,
1) CCSR 4-byte write to 0x00e00404, data=0x00000000
2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
BLOCK_SIZE=0x00014000
nand write <rcw image in memory> 0 <size of rcw image>
nand write <u-boot image in memory> 80000 <size of u-boot image>
Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
to match board NAND device with 4KB/page, block size 512KB.

1
board/freescale/ls2085ardb/MAINTAINERS
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@ -5,3 +5,4 @@ F: board/freescale/ls2085ardb/
F: board/freescale/ls2085a/ls2085ardb.c
F: include/configs/ls2085ardb.h
F: configs/ls2085ardb_defconfig
F: configs/ls2085ardb_nand_defconfig

4
board/freescale/ls2085ardb/ddr.c
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@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
return fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
#endif
return dram_size;
}

4
configs/ls2085ardb_nand_defconfig Normal file
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@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_TARGET_LS2085ARDB=y

40
include/configs/ls2085ardb.h
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@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RST_CTL_RESET_EN 0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RCW_SRC_NAND 0x119
#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (2048 * 1024)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SPL_PAD_TO 0x80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
@ -229,11 +264,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_FSL_MEMAC
#define CONFIG_PCI /* Enable PCIE */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */