net: macb: get DMA bus width from design config register
Get DMA bus width from design config register Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
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return config;
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}
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/*
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* Get the DMA bus width field of the network configuration register that we
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* should program. We find the width from decoding the design configuration
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* register to find the maximum supported data bus width.
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*/
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static u32 macb_dbw(struct macb_device *macb)
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{
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switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
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case 4:
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return GEM_BF(DBW, GEM_DBW128);
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case 2:
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return GEM_BF(DBW, GEM_DBW64);
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case 1:
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default:
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return GEM_BF(DBW, GEM_DBW32);
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}
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}
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int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
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{
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struct macb_device *macb;
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@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
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*/
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if (macb_is_gem(macb)) {
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ncfgr = gem_mdc_clk_div(id, macb);
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ncfgr |= GEM_BF(DBW, 1);
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ncfgr |= macb_dbw(macb);
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} else {
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ncfgr = macb_mdc_clk_div(id, macb);
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}
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@ -58,6 +58,9 @@
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#define MACB_WOL 0x00c4
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#define MACB_MID 0x00fc
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/* GEM specific register offsets */
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#define GEM_DCFG1 0x0280
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/* Bitfields in NCR */
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#define MACB_LB_OFFSET 0
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#define MACB_LB_SIZE 1
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@ -242,6 +245,14 @@
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#define MACB_IDNUM_SIZE 16
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/* Bitfields in DCFG1 */
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#define GEM_DBWDEF_OFFSET 25
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#define GEM_DBWDEF_SIZE 3
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/* constants for data bus width */
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#define GEM_DBW32 0
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#define GEM_DBW64 1
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#define GEM_DBW128 2
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/* Constants for CLK */
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#define MACB_CLK_DIV8 0
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#define MACB_CLK_DIV16 1
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