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imx: consolidate set_chipselect_size function

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Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.

While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2014-11-14 11:27:21 -02:00 committed by Stefano Babic
parent 53b7f18044
commit 32c81ea65c
5 changed files with 39 additions and 41 deletions
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31
arch/arm/cpu/armv7/mx5/soc.c
View File

@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr1);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr1);
}
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{

31
arch/arm/imx-common/cpu.c
View File

@ -187,3 +187,34 @@ void arch_preboot_os(void)
ipuv3_fb_shutdown();
}
#endif
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr[1]);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr[1]);
}

5
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -12,3 +12,8 @@
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3

12
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -202,11 +202,6 @@
*/
#define WBED 1
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
/*
* CSPI register definitions
*/
@ -414,8 +409,7 @@ struct weim {
#if defined(CONFIG_MX51)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
@ -424,9 +418,7 @@ struct iomuxc {
};
#elif defined(CONFIG_MX53)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr2;
u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;

1
arch/arm/include/asm/arch-mx6/sys_proto.h
View File

@ -26,6 +26,7 @@ u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.