ARM: mvebu: sync Armada-38x dts with Linux 4.20
Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes not taken are new compatible strings for the uart and nand flash controller. The nand binding is best updated if/when the mtd/nand infrastructure is updated. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
Stefan Roese
parent
2acc24fc28
commit
30c4383da3
@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 380 SoC.
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*
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@ -6,44 +7,6 @@
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
|
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* files (the "Software"), to deal in the Software without
|
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
|
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* sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "armada-38x.dtsi"
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@ -71,7 +34,7 @@
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};
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};
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pcie-controller {
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pcie {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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@ -104,6 +67,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <0>;
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@ -122,6 +86,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <1>;
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@ -140,6 +105,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <2>;
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@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 385 SoC.
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*
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@ -6,44 +7,6 @@
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
|
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
|
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "armada-38x.dtsi"
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@ -70,13 +33,7 @@
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};
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soc {
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internal-regs {
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pinctrl@18000 {
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compatible = "marvell,mv88f6820-pinctrl";
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};
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};
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pcie-controller {
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pciec: pcie {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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@ -106,7 +63,7 @@
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* configured in x4 by the bootloader, then
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* pcie@4,0 is not available.
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*/
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pcie@1,0 {
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pcie1: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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@ -115,6 +72,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <0>;
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@ -124,7 +82,7 @@
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};
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/* x1 port */
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pcie@2,0 {
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pcie2: pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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@ -133,6 +91,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <1>;
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@ -142,7 +101,7 @@
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};
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/* x1 port */
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pcie@3,0 {
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pcie3: pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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@ -151,6 +110,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <2>;
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@ -163,7 +123,7 @@
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* x1 port only available when pcie@1,0 is
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* configured as a x1 port
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*/
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pcie@4,0 {
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pcie4: pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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@ -172,6 +132,7 @@
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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marvell,pcie-port = <3>;
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@ -182,3 +143,7 @@
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};
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};
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};
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&pinctrl {
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compatible = "marvell,mv88f6820-pinctrl";
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};
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@ -118,18 +118,7 @@
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status = "okay";
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};
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spi1: spi@10680 {
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/*
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* CS0: W25Q32
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* CS1:
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* CS2: mikrobus
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*/
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pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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usb0: usb3@f8000 {
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usb3@f8000 {
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/* CON7, USB-A port on back of device */
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status = "okay";
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};
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@ -322,6 +311,18 @@
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};
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};
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&spi1 {
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/*
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* Add SPI CS pins for clearfog:
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* CS0: W25Q32
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* CS1:
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* CS2: mikrobus
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*/
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pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*
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+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
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MPP18: gpio ? (pca9655 int?)
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@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 388 SoC.
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*
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@ -5,39 +6,6 @@
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
|
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
|
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* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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* The main difference with the Armada 385 is that the 388 can handle two more
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* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
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* property and the name of the SoC, and add the second SATA host which control
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@ -50,13 +18,8 @@
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model = "Marvell Armada 388 family SoC";
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compatible = "marvell,armada388", "marvell,armada385",
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"marvell,armada380";
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soc {
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internal-regs {
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pinctrl@18000 {
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compatible = "marvell,mv88f6828-pinctrl";
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};
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sata@e0000 {
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compatible = "marvell,armada-380-ahci";
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reg = <0xe0000 0x2000>;
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@ -68,3 +31,7 @@
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};
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};
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};
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&pinctrl {
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compatible = "marvell,mv88f6828-pinctrl";
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};
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@ -72,40 +72,6 @@
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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spi0: spi@10600 {
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status = "okay";
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sc16is741: sc16is741@0 {
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compatible = "nxp,sc16is741";
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reg = <0>;
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clocks = <&sc16isclk>;
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spi-max-frequency = <4000000>;
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interrupt-parent = <&gpio0>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi1: spi@10680 {
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status = "okay";
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q016a", "spi-flash";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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spi-flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a11", "spi-flash";
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reg = <1>; /* Chip select 1 */
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spi-max-frequency = <108000000>;
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u-boot,dm-pre-reloc;
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};
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};
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I2C0: i2c@11000 {
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status = "okay";
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clock-frequency = <1000000>;
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@ -586,3 +552,37 @@
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};
|
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};
|
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};
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&spi0 {
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status = "okay";
|
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sc16is741: sc16is741@0 {
|
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compatible = "nxp,sc16is741";
|
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reg = <0>;
|
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clocks = <&sc16isclk>;
|
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spi-max-frequency = <4000000>;
|
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interrupt-parent = <&gpio0>;
|
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
};
|
||||
};
|
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|
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&spi1 {
|
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status = "okay";
|
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u-boot,dm-pre-reloc;
|
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spi-flash@0 {
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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compatible = "n25q016a", "spi-flash";
|
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reg = <0>; /* Chip select 0 */
|
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spi-max-frequency = <108000000>;
|
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};
|
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spi-flash@1 {
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#address-cells = <1>;
|
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#size-cells = <1>;
|
||||
compatible = "n25q128a11", "spi-flash";
|
||||
reg = <1>; /* Chip select 1 */
|
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spi-max-frequency = <108000000>;
|
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u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,3 +1,4 @@
|
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 38x family of SoCs.
|
||||
*
|
||||
@ -6,44 +7,6 @@
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
@ -83,7 +46,7 @@
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
devbus_bootcs: devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
@ -93,7 +56,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
devbus_cs0: devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
@ -103,7 +66,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
devbus_cs1: devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
@ -113,7 +76,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
devbus_cs2: devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
@ -123,7 +86,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
devbus_cs3: devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
@ -145,6 +108,10 @@
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,double-linefill-incr = <0>;
|
||||
arm,double-linefill-wrap = <0>;
|
||||
arm,double-linefill = <0>;
|
||||
prefetch-data = <1>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
@ -152,6 +119,13 @@
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xc200 0x20>;
|
||||
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
@ -168,32 +142,8 @@
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -204,7 +154,7 @@
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -258,19 +208,6 @@
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
|
||||
"mpp38", "mpp28", "mpp40", "mpp42",
|
||||
"mpp35", "mpp36", "mpp25", "mpp30",
|
||||
"mpp32";
|
||||
marvell,function = "dev";
|
||||
};
|
||||
|
||||
nand_rb: nand-rb {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "nand";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp4", "mpp5";
|
||||
marvell,function = "ge";
|
||||
@ -298,6 +235,20 @@
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp22", "mpp34", "mpp23",
|
||||
"mpp33", "mpp38", "mpp28",
|
||||
"mpp40", "mpp42", "mpp35",
|
||||
"mpp36", "mpp25", "mpp30",
|
||||
"mpp32";
|
||||
marvell,function = "dev";
|
||||
};
|
||||
|
||||
nand_rb: nand-rb {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "nand";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
@ -338,34 +289,42 @@
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
systemc: system-controller@18200 {
|
||||
compatible = "marvell,armada-380-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
@ -386,7 +345,8 @@
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>,
|
||||
<0x20250 0x8>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
@ -399,7 +359,7 @@
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
timer: timer@20300 {
|
||||
compatible = "marvell,armada-380-timer",
|
||||
"marvell,armada-xp-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
@ -413,14 +373,14 @@
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
watchdog: watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
cpurst: cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
@ -430,16 +390,37 @@
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
coherencyfab: coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
pmsu: pmsu@22000 {
|
||||
compatible = "marvell,armada-380-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* As a special exception to the "order by
|
||||
* register address" rule, the eth0 node is
|
||||
* placed here to ensure that it gets
|
||||
* registered as the first interface, since
|
||||
* the network subsystem doesn't allow naming
|
||||
* interfaces using DT aliases. Without this,
|
||||
* the ordering of interfaces is different
|
||||
* from the one used in U-Boot and the
|
||||
* labeling of interfaces on the boards, which
|
||||
* is very confusing for users.
|
||||
*/
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
tx-csum-limit = <9800>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
@ -456,7 +437,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
usb0: usb@58000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x58000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -464,8 +445,8 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
xor0: xor@60800 {
|
||||
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60a00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
@ -484,8 +465,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
xor1: xor@60900 {
|
||||
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
@ -504,14 +485,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -520,14 +493,29 @@
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
cesa: crypto@90000 {
|
||||
compatible = "marvell,armada-38x-crypto";
|
||||
reg = <0x90000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 23>, <&gateclk 21>,
|
||||
<&gateclk 14>, <&gateclk 16>;
|
||||
clock-names = "cesa0", "cesa1",
|
||||
"cesaz0", "cesaz1";
|
||||
marvell,crypto-srams = <&crypto_sram0>,
|
||||
<&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x800>;
|
||||
};
|
||||
|
||||
rtc: rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
ahci0: sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -535,7 +523,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
bm: bm@c8000 {
|
||||
compatible = "marvell,armada-380-neta-bm";
|
||||
reg = <0xc8000 0xac>;
|
||||
clocks = <&gateclk 13>;
|
||||
internal-mem = <&bm_bppi>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ahci1: sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -551,23 +547,23 @@
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
thermal: thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
reg = <0xe4078 0x4>, <0xe4070 0x8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
nand_controller: nand-controller@d0000 {
|
||||
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
sdhci: sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
@ -579,7 +575,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
usb3_0: usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -587,7 +583,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
usb3_1: usb3@f8000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -595,10 +591,63 @@
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
crypto_sram0: sa-sram0 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
|
||||
clocks = <&gateclk 23>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
|
||||
};
|
||||
|
||||
crypto_sram1: sa-sram1 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
|
||||
clocks = <&gateclk 21>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
|
||||
};
|
||||
|
||||
bm_bppi: bm-bppi {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&gateclk 13>;
|
||||
no-memory-wc;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
/* 1 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user