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Xilinx changes for v2023.01-rc1 (round 3)

Browse Source 
fpga:
 - Create new uclass
 - Get rid of FPGA_DEBUG and use logging infrastructure
 
 zynq:
 - Enable early EEPROM decoding
 - Some DT updates
 
 zynqmp:
 - Use OCM_BANK_0 to check config loading permission
 - Change config object loading in SPL
 - Some DT updates
 
 net:
 - emaclite: Enable driver for RISC-V
 
 xilinx:
 - Fix static checker warnings
 - Fix GCC12 warning
 
 sdhci:
 - Read PD id from DT
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Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT
This commit is contained in:
Tom Rini 2022-10-11 09:57:08 -04:00
commit 300077cf8c
35 changed files with 312 additions and 244 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -940,6 +940,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: drivers/fpga/
F: cmd/fpga.c
F: include/fpga.h
F: test/dm/fpga.c
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>

1
arch/arm/dts/versal-mini-emmc0.dts
View File

@ -44,7 +44,6 @@
reg = <0x0 0xf1040000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk200 &clk200>;
xlnx,device_id = <0>;
no-1-8-v;
xlnx,mio-bank = <0>;
};

1
arch/arm/dts/versal-mini-emmc1.dts
View File

@ -44,7 +44,6 @@
reg = <0x0 0xf1050000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk200 &clk200>;
xlnx,device_id = <1>;
no-1-8-v;
xlnx,mio-bank = <0>;
};

6
arch/arm/dts/zynq-zc702.dts
View File

@ -17,6 +17,8 @@
spi0 = &qspi;
mmc0 = &sdhci0;
usb0 = &usb0;
nvmem0 = &eeprom;
rtc0 = &rtc;
};
memory@0 {
@ -142,7 +144,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
eeprom: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
};
@ -164,7 +166,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};

6
arch/arm/dts/zynq-zc706.dts
View File

@ -16,6 +16,8 @@
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
nvmem0 = &eeprom;
rtc0 = &rtc;
};
memory@0 {
@ -101,7 +103,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
eeprom: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
};
@ -123,7 +125,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};

1
arch/arm/dts/zynqmp-mini-emmc0.dts
View File

@ -56,7 +56,6 @@
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <0>;
};
};
};

1
arch/arm/dts/zynqmp-mini-emmc1.dts
View File

@ -56,7 +56,6 @@
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <1>;
};
};
};

2
arch/arm/dts/zynqmp.dtsi
View File

@ -720,7 +720,6 @@
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0>;
iommus = <&smmu 0x870>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
@ -736,7 +735,6 @@
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <1>;
iommus = <&smmu 0x871>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";

6
arch/arm/mach-zynqmp/mp.c
View File

@ -163,7 +163,7 @@ static int check_r5_mode(void)
int cpu_disable(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
if (nr <= ZYNQMP_CORE_APU3) {
u32 val = readl(&crfapb_base->rst_fpd_apu);
val |= 1 << nr;
writel(val, &crfapb_base->rst_fpd_apu);
@ -176,7 +176,7 @@ int cpu_disable(u32 nr)
int cpu_status(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
if (nr <= ZYNQMP_CORE_APU3) {
u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
nr * 8);
@ -252,7 +252,7 @@ void initialize_tcm(bool mode)
int cpu_release(u32 nr, int argc, char *const argv[])
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
if (nr <= ZYNQMP_CORE_APU3) {
u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
/* HIGH */
writel((u32)(boot_addr >> 32),

4
arch/sandbox/dts/test.dts
View File

@ -652,6 +652,10 @@
};
};
fpga {
compatible = "sandbox,fpga";
};
pinctrl-gpio {
compatible = "sandbox,pinctrl-gpio";

9
board/xilinx/common/board.c
View File

@ -121,7 +121,7 @@ struct xilinx_legacy_format {
static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size)
{
int i;
char byte;
unsigned char byte;
for (i = 0; i < size; i++) {
byte = eeprom[i];
@ -460,8 +460,8 @@ int board_late_init_xilinx(void)
desc->serial);
if (desc->uuid[0]) {
char uuid[UUID_STR_LEN + 1];
char *t = desc->uuid;
unsigned char uuid[UUID_STR_LEN + 1];
unsigned char *t = desc->uuid;
memset(uuid, 0, UUID_STR_LEN + 1);
@ -476,9 +476,6 @@ int board_late_init_xilinx(void)
continue;
for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) {
if (!desc->mac_addr[i])
break;
if (is_valid_ethaddr((const u8 *)desc->mac_addr[i]))
ret |= eth_env_set_enetaddr_by_index("eth",
macid++, desc->mac_addr[i]);

1
board/xilinx/common/cpu-info.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <init.h>
#include <soc.h>
int print_cpuinfo(void)

3
board/xilinx/zynq/board.c
View File

@ -37,6 +37,9 @@ int board_init(void)
if (IS_ENABLED(CONFIG_SPL_BUILD))
printf("Silicon version:\t%d\n", zynq_get_silicon_version());
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
xilinx_read_eeprom();
return 0;
}

14
board/xilinx/zynqmp/zynqmp.c
View File

@ -145,6 +145,14 @@ int board_init(void)
char name[SOC_MAX_STR_SIZE];
int ret;
#endif
#if defined(CONFIG_SPL_BUILD)
/* Check *at build time* if the filename is an non-empty string */
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
zynqmp_pm_cfg_obj_size);
#endif
#if defined(CONFIG_ZYNQMP_FIRMWARE)
struct udevice *dev;
@ -154,10 +162,6 @@ int board_init(void)
#endif
#if defined(CONFIG_SPL_BUILD)
/* Check *at build time* if the filename is an non-empty string */
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
zynqmp_pm_cfg_obj_size);
printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
/* the CSU disables the JTAG interface when secure boot is enabled */
@ -607,7 +611,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
void set_dfu_alt_info(char *interface, char *devstr)
{
u8 multiboot;
int multiboot;
int bootseq = 0;
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);

2
drivers/clk/clk_versal.c
View File

@ -602,7 +602,7 @@ static void versal_get_clock_info(void)
}
}
int versal_clock_setup(void)
static int versal_clock_setup(void)
{
int ret;

11
drivers/firmware/firmware-zynqmp.c
View File

@ -82,7 +82,7 @@ int zynqmp_pmufw_node(u32 id)
ret = zynqmp_pmufw_load_config_object(xpm_configobject,
sizeof(xpm_configobject));
if (ret && id == NODE_APU_0)
if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0)
skip_config = true;
return 0;
@ -235,6 +235,8 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
*
* @cfg_obj: Pointer to the configuration object
* @size: Size of @cfg_obj in bytes
* Return: 0 on success otherwise negative errno. If the config object
* is not loadable returns positive errno XST_PM_NO_ACCESS(2002)
*/
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
{
@ -249,7 +251,10 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
printf("PMUFW no permission to change config object\n");
if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) {
printf("PMUFW: No permission to change config object\n");
return err;
}
return -EACCES;
}
@ -294,7 +299,7 @@ static int zynqmp_power_probe(struct udevice *dev)
ret & ZYNQMP_PM_VERSION_MINOR_MASK);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
zynqmp_pmufw_node(NODE_APU_0);
zynqmp_pmufw_node(NODE_OCM_BANK_0);
return 0;
};

37
drivers/fpga/ACEX1K.c
View File

@ -7,18 +7,14 @@
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*/
#define LOG_CATEGORY UCLASS_FPGA
#include <common.h> /* core U-Boot definitions */
#include <console.h>
#include <log.h>
#include <ACEX1K.h> /* ACEX device family */
#include <linux/delay.h>
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
@ -44,7 +40,7 @@ int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
log_debug("Launching Passive Serial Loader\n");
ret_val = ACEX1K_ps_load (desc, buf, bsize);
break;
@ -64,7 +60,7 @@ int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
log_debug("Launching Passive Serial Dump\n");
ret_val = ACEX1K_ps_dump (desc, buf, bsize);
break;
@ -93,8 +89,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
int i;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
size_t bytecount = 0;
@ -102,16 +97,16 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"clk:\t0x%p\n"
"data:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"clk:\t0x%p\n"
"data:\t0x%p\n"
"done:\t0x%p\n\n",
&fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...", cookie);
#endif

31
drivers/fpga/Kconfig
View File

@ -27,6 +27,12 @@ config FPGA_STRATIX_V
help
Say Y here to enable the Altera Stratix V FPGA specific driver.
config FPGA_ACEX1K
bool "Enable Altera ACEX 1K driver"
depends on FPGA_ALTERA
help
Say Y here to enable the Altera ACEX 1K FPGA specific driver.
config FPGA_CYCLON2
bool "Enable Altera FPGA driver for Cyclone II"
depends on FPGA_ALTERA
@ -71,6 +77,12 @@ config FPGA_VERSALPL
Versal. The bitstream will only be generated as PDI for Versal
platform.
config FPGA_SPARTAN2
bool "Enable Spartan2 FPGA driver"
depends on FPGA_XILINX
help
Enable Spartan2 FPGA driver.
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
depends on FPGA_XILINX
@ -118,4 +130,23 @@ config SPL_FPGA_LOAD_SECURE
Enables the fpga loads() functions that are used to load secure
(authenticated or encrypted or both) bitstreams on to FPGA.
config DM_FPGA
bool "Enable Driver Model for FPGA drivers"
depends on DM
select FPGA
help
Enable driver model for Field-Programmable Gate Array (FPGA) devices.
The devices cover a wide range of applications and are configured at
runtime by loading a bitstream into the FPGA device.
Loading a bitstream from any kind of storage is the main task of the
FPGA drivers.
For now this uclass has no methods yet.
config SANDBOX_FPGA
bool "Enable sandbox FPGA driver"
depends on SANDBOX && DM_FPGA
help
This is a driver model based FPGA driver for sandbox.
Currently it is a stub only, as there are no usable uclass methods yet.
endmenu

3
drivers/fpga/Makefile
View File

@ -4,6 +4,9 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += fpga.o
obj-$(CONFIG_DM_FPGA) += fpga-uclass.o
obj-$(CONFIG_SANDBOX_FPGA) += sandbox.o
obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o

11
drivers/fpga/altera.c
View File

@ -7,6 +7,8 @@
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*/
#define LOG_CATEGORY UCLASS_FPGA
/*
* Altera FPGA support
*/
@ -16,9 +18,6 @@
#include <log.h>
#include <stratixII.h>
/* Define FPGA_DEBUG to 1 to get debug printf's */
#define FPGA_DEBUG 0
static const struct altera_fpga {
enum altera_family family;
const char *name;
@ -106,8 +105,7 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
if (!fpga)
return FPGA_FAIL;
debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
__func__, fpga->name);
log_debug("Launching the %s Loader...\n", fpga->name);
if (fpga->load)
return fpga->load(desc, buf, bsize);
return 0;
@ -120,8 +118,7 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
if (!fpga)
return FPGA_FAIL;
debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
__func__, fpga->name);
log_debug("Launching the %s Reader...\n", fpga->name);
if (fpga->dump)
return fpga->dump(desc, buf, bsize);
return 0;

38
drivers/fpga/cyclon2.c
View File

@ -5,18 +5,14 @@
* Based on ACE1XK.c
*/
#define LOG_CATEGORY UCLASS_FPGA
#include <common.h> /* core U-Boot definitions */
#include <log.h>
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
#include <linux/delay.h>
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
#define PRINTF(fmt, args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
@ -42,7 +38,7 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case passive_serial:
PRINTF("%s: Launching Passive Serial Loader\n", __func__);
log_debug("Launching Passive Serial Loader\n");
ret_val = CYC2_ps_load(desc, buf, bsize);
break;
@ -51,8 +47,7 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
* done in the write() callback. Use the existing PS load
* function for FPP, too.
*/
PRINTF("%s: Launching Fast Passive Parallel Loader\n",
__func__);
log_debug("Launching Fast Passive Parallel Loader\n");
ret_val = CYC2_ps_load(desc, buf, bsize);
break;
@ -72,7 +67,7 @@ int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case passive_serial:
PRINTF("%s: Launching Passive Serial Dump\n", __func__);
log_debug("Launching Passive Serial Dump\n");
ret_val = CYC2_ps_dump(desc, buf, bsize);
break;
@ -99,22 +94,21 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
int ret = 0;
PRINTF("%s: start with interface functions @ 0x%p\n",
__func__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"write:\t0x%p\n"
"done:\t0x%p\n\n",
__func__, &fn, fn, fn->config, fn->status,
fn->write, fn->done);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"write:\t0x%p\n"
"done:\t0x%p\n\n",
&fn, fn, fn->config, fn->status,
fn->write, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf("Loading FPGA Device %d...", cookie);
#endif

11
drivers/fpga/fpga-uclass.c Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Alexander Dahl <post@lespocky.de>
*/
#include <dm.h>
UCLASS_DRIVER(fpga) = {
.name = "fpga",
.id = UCLASS_FPGA,
};

17
drivers/fpga/sandbox.c Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Alexander Dahl <post@lespocky.de>
*/
#include <dm.h>
static const struct udevice_id sandbox_fpga_match[] = {
{ .compatible = "sandbox,fpga" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(sandbox_fpga) = {
.name = "sandbox_fpga",
.id = UCLASS_FPGA,
.of_match = sandbox_fpga_match,
};

82
drivers/fpga/spartan2.c
View File

@ -4,15 +4,11 @@
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*/
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
#define LOG_CATEGORY UCLASS_FPGA
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#include <common.h> /* core U-Boot definitions */
#include <log.h>
#include <spartan2.h> /* Spartan-II device family */
#undef CONFIG_SYS_FPGA_CHECK_BUSY
@ -46,12 +42,12 @@ static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
log_debug("Launching Slave Serial Load\n");
ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
log_debug("Launching Slave Parallel Load\n");
ret_val = spartan2_sp_load(desc, buf, bsize);
break;
@ -69,12 +65,12 @@ static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
log_debug("Launching Slave Serial Dump\n");
ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
log_debug("Launching Slave Parallel Dump\n");
ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
@ -100,8 +96,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
int ret_val = FPGA_FAIL; /* assume the worst */
xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
size_t bytecount = 0;
@ -109,24 +104,24 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n",
"post:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n"
"post:\t0x%p\n\n",
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
/*
* This code is designed to emulate the "Express Style"
@ -302,8 +297,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
int i;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
size_t bytecount = 0;
@ -311,16 +305,16 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
&fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif

82
drivers/fpga/spartan3.c
View File

@ -9,15 +9,11 @@
* on spartan2.c (Rich Ireland, rireland@enterasys.com).
*/
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
#define LOG_CATEGORY UCLASS_FPGA
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#include <common.h> /* core U-Boot definitions */
#include <log.h>
#include <spartan3.h> /* Spartan-II device family */
#undef CONFIG_SYS_FPGA_CHECK_BUSY
@ -51,12 +47,12 @@ static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
log_debug("Launching Slave Serial Load\n");
ret_val = spartan3_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
log_debug("Launching Slave Parallel Load\n");
ret_val = spartan3_sp_load(desc, buf, bsize);
break;
@ -74,12 +70,12 @@ static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
log_debug("Launching Slave Serial Dump\n");
ret_val = spartan3_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
log_debug("Launching Slave Parallel Dump\n");
ret_val = spartan3_sp_dump(desc, buf, bsize);
break;
@ -105,8 +101,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
int ret_val = FPGA_FAIL; /* assume the worst */
xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
size_t bytecount = 0;
@ -114,24 +109,24 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n",
"post:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n"
"post:\t0x%p\n\n",
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
/*
* This code is designed to emulate the "Express Style"
@ -309,8 +304,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
int i;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
log_debug("start with interface functions @ 0x%p\n", fn);
if (fn) {
size_t bytecount = 0;
@ -318,16 +312,16 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
log_debug("Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
&fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif

69
drivers/fpga/virtex2.c
View File

@ -12,21 +12,14 @@
* on spartan2.c (Rich Ireland, rireland@enterasys.com).
*/
#define LOG_CATEGORY UCLASS_FPGA
#include <common.h>
#include <console.h>
#include <log.h>
#include <virtex2.h>
#include <linux/delay.h>
#if 0
#define FPGA_DEBUG
#endif
#ifdef FPGA_DEBUG
#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
#define PRINTF(fmt, args...)
#endif
/*
* If the SelectMap interface can be overrun by the processor, define
* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
@ -89,12 +82,12 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
switch (desc->iface) {
case slave_serial:
PRINTF("%s: Launching Slave Serial Load\n", __func__);
log_debug("Launching Slave Serial Load\n");
ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF("%s: Launching Slave Parallel Load\n", __func__);
log_debug("Launching Slave Parallel Load\n");
ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
@ -111,12 +104,12 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case slave_serial:
PRINTF("%s: Launching Slave Serial Dump\n", __func__);
log_debug("Launching Slave Serial Dump\n");
ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
log_debug("Launching Slave Parallel Dump\n");
ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
@ -150,8 +143,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
{
unsigned long ts;
PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
__func__, __LINE__, fn);
log_debug("Start with interface functions @ 0x%p\n", fn);
if (!fn) {
printf("%s:%d: NULL Interface function table!\n",
@ -160,25 +152,24 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
}
/* Gotta split this one up (so the stack won't blow??) */
PRINTF("%s:%d: Function Table:\n"
" base 0x%p\n"
" struct 0x%p\n"
" pre 0x%p\n"
" prog 0x%p\n"
" init 0x%p\n"
" error 0x%p\n",
__func__, __LINE__,
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
PRINTF(" clock 0x%p\n"
" cs 0x%p\n"
" write 0x%p\n"
" rdata 0x%p\n"
" wdata 0x%p\n"
" busy 0x%p\n"
" abort 0x%p\n"
" post 0x%p\n\n",
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
fn->busy, fn->abort, fn->post);
log_debug("Function Table:\n"
" base 0x%p\n"
" struct 0x%p\n"
" pre 0x%p\n"
" prog 0x%p\n"
" init 0x%p\n"
" error 0x%p\n",
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
log_debug(" clock 0x%p\n"
" cs 0x%p\n"
" write 0x%p\n"
" rdata 0x%p\n"
" wdata 0x%p\n"
" busy 0x%p\n"
" abort 0x%p\n"
" post 0x%p\n\n",
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
fn->busy, fn->abort, fn->post);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf("Initializing FPGA Device %d...\n", cookie);
@ -330,8 +321,8 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
if ((*fn->done)(cookie) == FPGA_SUCCESS) {
PRINTF("%s:%d:done went active early, bytecount = %d\n",
__func__, __LINE__, bytecount);
log_debug("done went active early, bytecount = %zu\n",
bytecount);
break;
}
@ -465,8 +456,8 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
if ((*fn->done)(cookie) == FPGA_SUCCESS) {
PRINTF("%s:%d:done went active early, bytecount = %d\n",
__func__, __LINE__, bytecount);
log_debug("done went active early, bytecount = %zu\n",
bytecount);
break;
}

53
drivers/mmc/zynq_sdhci.c
View File

@ -61,7 +61,7 @@ struct arasan_sdhci_plat {
struct arasan_sdhci_priv {
struct sdhci_host *host;
struct arasan_sdhci_clk_data clk_data;
u8 deviceid;
u32 node_id;
u8 bank;
u8 no_1p8;
struct reset_ctl_bulk resets;
@ -111,7 +111,7 @@ static const u8 mode2timing[] = {
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
};
static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
{
int ret;
@ -155,7 +155,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
if (ret)
return ret;
} else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_INPUT, itap_delay, NULL);
}
@ -163,7 +163,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
return 0;
}
static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
@ -174,13 +174,13 @@ static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
(otap_delay << 16));
} else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_OUTPUT, otap_delay, NULL);
}
}
static inline int zynqmp_dll_reset(u8 node_id, u32 type)
static inline int zynqmp_dll_reset(u32 node_id, u32 type)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
@ -192,12 +192,12 @@ static inline int zynqmp_dll_reset(u8 node_id, u32 type)
type == PM_DLL_RESET_ASSERT ?
SD1_DLL_RST : 0);
} else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SD_DLL_RESET, type, 0, NULL);
}
}
static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id)
{
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
@ -250,7 +250,6 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
dev_dbg(mmc->dev, "%s\n", __func__);
@ -262,7 +261,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
mdelay(1);
arasan_zynqmp_dll_reset(host, node_id);
arasan_zynqmp_dll_reset(host, priv->node_id);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
@ -308,7 +307,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
}
udelay(1);
arasan_zynqmp_dll_reset(host, node_id);
arasan_zynqmp_dll_reset(host, priv->node_id);
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
@ -334,7 +333,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
int ret;
@ -374,14 +372,14 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
/* Set the Clock Phase */
ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
ret = arasan_zynqmp_set_out_tapdelay(priv->node_id, tap_delay);
if (ret) {
dev_err(dev, "Error setting output Tap Delay\n");
return ret;
}
/* Release DLL Reset */
ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_RELEASE);
if (ret) {
dev_err(dev, "dll_reset release failed with err: %d\n", ret);
return ret;
@ -405,7 +403,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
int ret;
@ -419,7 +416,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
return 0;
/* Assert DLL Reset */
ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_ASSERT);
if (ret) {
dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
return ret;
@ -451,7 +448,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
/* Limit input tap_delay value to 8 bits */
tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
ret = arasan_zynqmp_set_in_tapdelay(priv->node_id, tap_delay);
if (ret) {
dev_err(dev, "Error setting Input Tap Delay\n");
return ret;
@ -717,14 +714,14 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
struct udevice *dev)
{
int ret;
u32 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
struct clk clk;
unsigned long clock, mhz;
ret = xilinx_pm_request(PM_REQUEST_NODE, node_id, ZYNQMP_PM_CAPABILITY_ACCESS,
ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_NO, NULL);
ret = xilinx_pm_request(PM_REQUEST_NODE, priv->node_id,
ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
ZYNQMP_PM_REQUEST_ACK_NO, NULL);
if (ret) {
dev_err(dev, "Request node failed for %d\n", node_id);
dev_err(dev, "Request node failed for %d\n", priv->node_id);
return ret;
}
@ -743,13 +740,13 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
return ret;
}
ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0);
ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_FIXED, 0);
if (ret) {
dev_err(dev, "SD_CONFIG_FIXED failed\n");
return ret;
}
ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL,
ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_EMMC_SEL,
dev_read_bool(dev, "non-removable"));
if (ret) {
dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n");
@ -779,13 +776,13 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
else
mhz = 25;
ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_BASECLK, mhz);
if (ret) {
dev_err(dev, "SD_CONFIG_BASECLK failed\n");
return ret;
}
ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT,
ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_8BIT,
(dev_read_u32_default(dev, "bus-width", 1) == 8));
if (ret) {
dev_err(dev, "SD_CONFIG_8BIT failed\n");
@ -900,6 +897,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
static int arasan_sdhci_of_to_plat(struct udevice *dev)
{
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
u32 pm_info[2];
priv->host = calloc(1, sizeof(struct sdhci_host));
if (!priv->host)
@ -916,10 +914,13 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
if (IS_ERR(priv->host->ioaddr))
return PTR_ERR(priv->host->ioaddr);
priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
priv->node_id = 0;
if (!dev_read_u32_array(dev, "power-domains", pm_info, ARRAY_SIZE(pm_info)))
priv->node_id = pm_info[1];
return 0;
}

5
drivers/net/xilinx_axi_emac.c
View File

@ -11,6 +11,7 @@
#include <cpu_func.h>
#include <display_options.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
#include <net.h>
#include <malloc.h>
@ -317,6 +318,10 @@ static int axiemac_phy_init(struct udevice *dev)
/* Interface - look at tsec */
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
if (IS_ERR_OR_NULL(phydev)) {
dev_err(dev, "phy_connect() failed\n");
return -ENODEV;
}
phydev->supported &= supported;
phydev->advertising = phydev->supported;

20
drivers/net/xilinx_emaclite.c
View File

@ -14,14 +14,13 @@
#include <console.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <eth_phy.h>
DECLARE_GLOBAL_DATA_PTR;
@ -113,12 +112,12 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
/* Word aligned buffer, no correction needed. */
to32ptr = (u32 *) destptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
*to32ptr++ = __raw_readl(from32ptr++);
bytecount -= 4;
}
to8ptr = (u8 *) to32ptr;
alignbuffer = *from32ptr++;
alignbuffer = __raw_readl(from32ptr++);
from8ptr = (u8 *) &alignbuffer;
for (i = 0; i < bytecount; i++)
@ -136,8 +135,7 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
from32ptr = (u32 *) srcptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
__raw_writel(*from32ptr++, to32ptr++);
bytecount -= 4;
}
@ -148,7 +146,7 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
for (i = 0; i < bytecount; i++)
*to8ptr++ = *from8ptr++;
*to32ptr++ = alignbuffer;
__raw_writel(alignbuffer, to32ptr++);
}
static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
@ -519,6 +517,8 @@ try_again:
length = ntohs(ip->ip_len);
length += ETHER_HDR_SIZE + ETH_FCS_LEN;
debug("IP Packet %x\n", length);
if (length > PKTSIZE)
length = PKTSIZE;
break;
default:
debug("Other Packet\n");
@ -527,7 +527,7 @@ try_again:
}
/* Read the rest of the packet which is longer then first read */
if (length != first_read)
if (length > first_read)
xemaclite_alignedread(addr + first_read,
etherrxbuff + first_read,
length - first_read);
@ -615,8 +615,8 @@ static int emaclite_of_to_plat(struct udevice *dev)
int offset = 0;
pdata->iobase = dev_read_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
emaclite->regs = (struct emaclite_regs *)ioremap(pdata->iobase,
0x10000);
emaclite->phyaddr = -1;

2
drivers/net/zynq_gem.c
View File

@ -328,7 +328,7 @@ static int zynq_phy_init(struct udevice *dev)
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
if (!priv->phydev)
if (IS_ERR_OR_NULL(priv->phydev))
return -ENODEV;
if (priv->max_speed) {

2
drivers/soc/soc_xilinx_zynqmp.c
View File

@ -285,7 +285,7 @@ static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size
return snprintf(buf, size, "%s", priv->family);
}
int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size)
static int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size)
{
struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
const char *machine = priv->machine;

2
drivers/spi/zynqmp_gqspi.c
View File

@ -294,7 +294,7 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);

1
include/dm/uclass-id.h
View File

@ -56,6 +56,7 @@ enum uclass_id {
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE, /* Firmware */
UCLASS_FPGA, /* FPGA device */
UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */

1
test/dm/Makefile
View File

@ -47,6 +47,7 @@ ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
endif
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_FPGA) += fpga.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_SOUND) += i2s.o

20
test/dm/fpga.c Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Alexander Dahl <post@lespocky.de>
*/
#include <dm.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
static int dm_test_fpga(struct unit_test_state *uts)
{
struct udevice *dev;
ut_assertok(uclass_first_device_err(UCLASS_FPGA, &dev));
return 0;
}
DM_TEST(dm_test_fpga, UT_TESTF_SCAN_FDT);