Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts
This commit is contained in:
Tom Rini
@@ -319,6 +319,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
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avnet-ultra96-rev1.dtb \
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avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
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zynqmp-a2197-revA.dtb \
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zynqmp-dlc21-revA.dtb \
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zynqmp-e-a2197-00-revA.dtb \
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zynqmp-g-a2197-00-revA.dtb \
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zynqmp-m-a2197-01-revA.dtb \
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221
arch/arm/dts/zynqmp-dlc21-revA.dts
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221
arch/arm/dts/zynqmp-dlc21-revA.dts
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@@ -0,0 +1,221 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP DLC21 revA
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*
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* (C) Copyright 2019 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <include/dt-bindings/gpio/gpio.h>
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/ {
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model = "Smartlynq+ DLC21 RevA";
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compatible = "xlnx,zynqmp-dlc21-revA", "xlnx,zynqmp-dlc21",
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"xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial2 = &dcc;
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usb0 = &usb0;
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usb1 = &usb1;
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spi0 = &spi0;
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nvmem0 = &eeprom;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0 0 0 0x80000000>, <0x8 0 0x3 0x80000000>;
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};
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si5332_1: si5332_1 { /* clk0_sgmii - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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si5332_2: si5332_2 { /* clk1_usb - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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xlnx,mio_bank = <0>;
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};
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&sdhci1 { /* sd1 MIO45-51 cd in place */
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status = "okay";
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no-1-8-v;
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disable-wp;
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xlnx,mio_bank = <1>;
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};
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&psgtr {
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status = "okay";
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/* sgmii, usb3 */
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clocks = <&si5332_1>, <&si5332_2>;
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clock-names = "ref0", "ref1";
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii"; /* DTG generates this properly 1512 */
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is-internal-pcspma;
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/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "", "", "", "", "", /* 0 - 4 */
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"", "", "", "", "", /* 5 - 9 */
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"", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
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"", "DISP_SCL", "DISP_DC_B", "DISP_RES_B", "DISP_CS_B", /* 25 - 29 */
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"", "DISP_SDI", "SYSTEM_RST_R_B", "", "I2C0_SCL", /* 30 - 34 */
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"I2C0_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
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"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
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"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
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"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
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"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
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"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 -89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
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"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
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"SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
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"", "", "", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
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"SYSCTLR_UTIL_2V5_EN", "", "", "", "", /* 125 - 129 */
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"", "", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "", /* 130 - 134 */
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"", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
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"", "", "SYSCTLR_ETH_RESET_B", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&i2c0 { /* MIO34/35 */
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status = "okay";
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clock-frequency = <400000>;
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jtag_vref: mcp4725@62 {
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compatible = "microchip,mcp4725";
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reg = <0x62>;
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vref-millivolt = <3300>;
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};
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eeprom: eeprom@50 { /* u46 */
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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/* u138 - TUSB320IRWBR - for USB-C */
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};
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&usb0 {
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status = "okay";
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xlnx,usb-polarity = <0>;
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xlnx,usb-reset-mode = <0>;
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "peripheral";
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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maximum-speed = "super-speed";
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phy-names = "usb3-phy";
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phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
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};
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&usb1 {
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status = "disabled"; /* Any unknown issue with USB-C */
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xlnx,usb-polarity = <0>;
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xlnx,usb-reset-mode = <0>;
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};
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&dwc3_1 {
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/delete-property/ phy-names ;
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/delete-property/ phys ;
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dr_mode = "host";
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk ;
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snps,dis_u3_susphy_quirk ;
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status = "okay";
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};
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&xilinx_ams {
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status = "okay";
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};
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&ams_ps {
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status = "okay";
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};
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&ams_pl {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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is-decoded-cs = <0>;
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num-cs = <1>;
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u-boot,dm-pre-reloc;
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displayspi@0 {
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compatible = "syncoam,seps525";
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u-boot,dm-pre-reloc;
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reg = <0>;
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status = "okay";
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spi-max-frequency = <10000000>;
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spi-cpol;
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spi-cpha;
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rotate = <0>;
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fps = <50>;
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buswidth = <8>;
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txbuflen = <64000>;
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reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>;
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dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>;
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debug = <0>;
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};
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};
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@@ -46,7 +46,7 @@
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si5332_1: si5332_1 { /* clk0_sgmii - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33333333>; /* FIXME */
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clock-frequency = <125000000>;
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};
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si5332_2: si5332_2 { /* clk1_usb - u142 */
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@@ -25,6 +25,7 @@ config SPL_SPI
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default y if ZYNQ_QSPI
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config SYS_BOARD
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string "Board name"
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default "zynqmp"
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config SYS_VENDOR
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@@ -149,6 +150,14 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
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Overwrite bootmode selected via boot mode pins to tell SPL what should
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be the next boot device.
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config SPL_ZYNQMP_RESTORE_JTAG
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bool "Restore JTAG"
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depends on SPL
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help
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Booting SPL in secure mode causes the CSU to disable the JTAG interface
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even if no eFuses were burnt. This option restores the interface if
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possible.
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config ZYNQ_SDHCI_MAX_FREQ
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default 200000000
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@@ -39,20 +39,26 @@
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#define RESET_REASON_INTERNAL BIT(1)
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#define RESET_REASON_EXTERNAL BIT(0)
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#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002
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#define CRLAPB_RST_LPD_DBG_RESET 0
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struct crlapb_regs {
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u32 reserved0[36];
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u32 cpu_r5_ctrl; /* 0x90 */
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u32 reserved1[37];
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u32 reserved1[7];
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u32 dbg_lpd_ctrl; /* 0xB0 */
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u32 reserved2[29];
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u32 timestamp_ref_ctrl; /* 0x128 */
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u32 reserved2[53];
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u32 reserved3[53];
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u32 boot_mode; /* 0x200 */
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u32 reserved3_0[7];
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u32 reserved4_0[7];
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u32 reset_reason; /* 0x220 */
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u32 reserved3_1[6];
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u32 reserved4_1[6];
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u32 rst_lpd_top; /* 0x23C */
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u32 reserved4[4];
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u32 rst_lpd_dbg; /* 0x240 */
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u32 reserved5[3];
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u32 boot_pin_ctrl; /* 0x250 */
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u32 reserved5[21];
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u32 reserved6[21];
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};
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
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@@ -141,12 +147,23 @@ struct apu_regs {
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#define ZYNQMP_SILICON_VER_MASK 0xF
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#define ZYNQMP_SILICON_VER_SHIFT 0
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#define CSU_JTAG_SEC_GATE_DISABLE GENMASK(7, 0)
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#define CSU_JTAG_DAP_ENABLE_DEBUG GENMASK(7, 0)
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#define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0)
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#define CSU_PCAP_PROG_RELEASE_PL BIT(0)
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struct csu_regs {
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u32 reserved0[4];
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u32 multi_boot;
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u32 reserved1[11];
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u32 reserved1[7];
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u32 jtag_chain_status_wr;
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u32 jtag_chain_status;
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u32 jtag_sec;
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u32 jtag_dap_cfg;
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u32 idcode;
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u32 version;
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u32 reserved2[3055];
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u32 pcap_prog;
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};
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#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
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