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mpc83xx: Cleanup usage of DDR constants

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:29 -05:00 committed by Kim Phillips
parent 72cd4087c9
commit 2fef402097
15 changed files with 150 additions and 50 deletions
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9
arch/powerpc/cpu/mpc83xx/spd_sdram.c
View File

@ -46,10 +46,19 @@ void board_add_ram_info(int use_default)
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
puts(", 32-bit");
else
puts(", unknown width");
#else
if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
puts(", 32-bit");
else
puts(", 64-bit");
#endif
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
puts(", ECC on");

5
include/configs/MPC8308RDB.h
View File

@ -149,7 +149,8 @@
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
@ -184,7 +185,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */

10
include/configs/MPC8313ERDB.h
View File

@ -131,7 +131,8 @@
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
| 0x00010000 /* TODO */ \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
@ -169,12 +170,13 @@
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32)
| SDRAM_CFG_DBW_32 \
| SDRAM_CFG_2T_EN)
/* 0x43088000 */
#else
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000

5
include/configs/MPC8315ERDB.h
View File

@ -141,7 +141,8 @@
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
@ -177,7 +178,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \

2
include/configs/MPC8323ERDB.h
View File

@ -78,7 +78,6 @@
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
@ -90,7 +89,6 @@
*/
#define CONFIG_SYS_DDR_SIZE 64 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ACS \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_9)
/* 0x80010101 */

52
include/configs/MPC832XEMDS.h
View File

@ -111,17 +111,53 @@
/* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
| CSCONFIG_ODT_WR_CFG \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80840102 */
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
| (13 << TIMING_CFG1_REFREC_SHIFT) \
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3935D322 */
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (31 << TIMING_CFG2_CPO_SHIFT) \
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x0F9048CA */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
#define CONFIG_SYS_DDR_MODE 0x44400232
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
| (0x0232 << SDRAM_MODE_SD_SHIFT))
/* 0x44400232 */
#define CONFIG_SYS_DDR_MODE2 0x8000c000
#define CONFIG_SYS_DDR_INTERVAL 0x03200064
#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#endif

7
include/configs/MPC8360ERDK.h
View File

@ -96,7 +96,10 @@
/*
* DDRCDR - DDR Control Driver Register
*/
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
| DDRCDR_ODT \
| DDRCDR_Q_DRN)
/* 0x80080001 */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
@ -109,7 +112,7 @@
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10 \
| CSCONFIG_ODT_WR_ACS)
| CSCONFIG_ODT_WR_ONLY_CURRENT)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_ECC_EN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000

8
include/configs/MPC837XEMDS.h
View File

@ -128,7 +128,10 @@
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
| DDRCDR_ODT \
| DDRCDR_Q_DRN)
/* 0x80080001 */ /* ODT 150ohm on SoC */
#undef CONFIG_DDR_ECC /* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
@ -147,7 +150,8 @@
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
| CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_14 \
| CSCONFIG_COL_BIT_10)
/* 0x80010202 */

26
include/configs/MPC837XERDB.h
View File

@ -166,8 +166,10 @@
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
@ -178,7 +180,6 @@
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
/* 0x00260802 */ /* DDR400 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
@ -188,9 +189,15 @@
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3935d322 */
/* 0x3937d322 */
#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x02984cc8 */
#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
@ -198,12 +205,13 @@
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32)
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE \
| SDRAM_CFG_2T_EN)
/* 0x43088000 */
#else
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
| SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
#endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */

5
include/configs/MVBLM7.h
View File

@ -72,7 +72,10 @@
#define CONFIG_SYS_MEMTEST_END (70<<20)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDRCDR 0x22000001
#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
| DDRCDR_NZ_HIZ \
| DDRCDR_Q_DRN)
/* 0x22000001 */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDR_SIZE 512

5
include/configs/kmeter1.h
View File

@ -72,9 +72,10 @@
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | \
CSCONFIG_ODT_WR_ACS)
CSCONFIG_ODT_WR_ONLY_CURRENT)
#define CONFIG_SYS_DDRCDR 0x40000001
#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
/* 0x40000001 */
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000

8
include/configs/mpc8308_p1m.h
View File

@ -157,8 +157,10 @@
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
@ -192,7 +194,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */

5
include/configs/ve8313.h
View File

@ -81,7 +81,8 @@
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
| 0x00040000 /* TODO */ \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ALL \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80840102 */
@ -118,7 +119,7 @@
/* 0x03202000 */
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE)
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \

9
include/configs/vme8349.h
View File

@ -106,10 +106,13 @@
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_DDRCDR 0x80080001
#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
| DDRCDR_ODT \
| DDRCDR_Q_DRN)
/* 0x80080001 */
/*
* FLASH on the Local Bus

32
include/mpc83xx.h
View File

@ -969,9 +969,29 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#define CSCONFIG_ODT_WR_ACS 0x00010000
#if defined(CONFIG_MPC832x)
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define CSCONFIG_ODT_RD_ALL 0x00400000
#define CSCONFIG_ODT_WR_NEVER 0x00000000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ALL 0x00040000
#elif defined(CONFIG_MPC832x)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
#define CSCONFIG_ODT_RD_ALL 0x00400000
#define CSCONFIG_ODT_WR_NEVER 0x00000000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
#define CSCONFIG_ODT_WR_ALL 0x00040000
#endif
#define CSCONFIG_BANK_BIT_3 0x00004000
#define CSCONFIG_ROW_BIT 0x00000700
@ -1071,8 +1091,16 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
#else
#define SDRAM_CFG_32_BE 0x00080000
#endif
#if !defined(CONFIG_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
#endif
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_HSE 0x00000008