Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig

In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things.  First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h.  This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.

With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available).  Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>

arch/arc/lib/cpu.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <malloc.h>
 #include <vsprintf.h>
@@ -18,7 +19,7 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+	gd->cpu_clk = get_board_sys_clk();
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -6,12 +6,13 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <asm/arch/ep93xx.h>
 #include <asm/io.h>
 #include <div64.h>
 
 /*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -20,14 +21,14 @@
 /*
  * return the PLL output frequency
  *
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
  * / (X2IPD + 1) / 2^PS
  */
 static ulong get_PLLCLK(uint32_t *pllreg)
 {
 	uint8_t i;
 	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	uint64_t rate = get_board_sys_clk();
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
 	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
@@ -87,9 +88,9 @@ ulong get_UCLK(void)
 
 	const uint32_t value = readl(&syscon->pwrcnt);
 	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = CONFIG_SYS_CLK_FREQ;
+		uclk_rate = get_board_sys_clk();
 	else
-		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+		uclk_rate = get_board_sys_clk() / 2;
 
 	return uclk_rate;
 }

arch/arm/cpu/arm920t/imx/speed.c

@@ -7,13 +7,14 @@
 
 #include <common.h>
 #if defined (CONFIG_IMX)
+#include <clock_legacy.h>
 
 #include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
  * SH FIXME: 16780000 in our case
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -45,7 +46,7 @@ ulong get_mcuPLLCLK(void)
 
 	mfi = mfi<=5 ? 5 : mfi;
 
-	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
 }
 
 ulong get_FCLK(void)

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -39,7 +39,7 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 
 	sys_info->freq_systembus = sysclk;
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -131,9 +131,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	sysclk_path = fdt_get_alias(blob, "sysclk");
 	if (sysclk_path)
 		do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
-				     CONFIG_SYS_CLK_FREQ, 1);
+				     get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
-			       "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+			       "clock-frequency", get_board_sys_clk(), 1);
 
 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 #define UBOOT_HEAD_LEN	0x1000

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <fsl_ddr_sdram.h>

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -161,7 +161,7 @@ void fsl_fdt_disable_usb(void *blob)
 	 * controller is used, SYSCLK must meet the additional requirement
 	 * of 100 MHz.
 	 */
-	if (CONFIG_SYS_CLK_FREQ != 100000000) {
+	if (get_board_sys_clk() != 100000000) {
 		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
 		while (off != -FDT_ERR_NOTFOUND) {
 			fdt_status_disabled(blob, off);
@@ -655,7 +655,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
-			     CONFIG_SYS_CLK_FREQ, 1);
+			     get_board_sys_clk(), 1);
 
 #ifdef CONFIG_GIC_V3_ITS
 	ls_gic_rd_tables_init(blob);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -52,12 +52,12 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
 #ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_CLUSTER_CLK_FREQ	get_board_sys_clk()
 #endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
 

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -72,7 +72,7 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <image.h>
 #include <log.h>

arch/arm/mach-davinci/cpu.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>

arch/arm/mach-exynos/clock.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <log.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -136,7 +137,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	/* SDIV [2:0] */
 	s = r & 0x7;
 
-	freq = CONFIG_SYS_CLK_FREQ;
+	freq = get_board_sys_clk();
 
 	if (pllreg == EPLL || pllreg == RPLL) {
 		k = k & 0xffff;
@@ -1051,7 +1052,7 @@ static unsigned long exynos5800_get_lcd_clk(void)
 									RPLL};
 		sclk = get_pll_clk(reg_map[sel]);
 	} else
-		sclk = CONFIG_SYS_CLK_FREQ;
+		sclk = get_board_sys_clk();
 	/*
 	 * CLK_DIV_DISP10
 	 * FIMD1_RATIO [3:0]

arch/nds32/cpu/n1213/ag101/timer.c

@@ -9,6 +9,7 @@
  */
 #ifndef CONFIG_TIMER
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <irq_func.h>
 #include <log.h>
@@ -76,7 +77,7 @@ void reset_timer_masked(void)
 	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 #else
 	lastdec = readl(&tmr->timer3_counter) /
-			(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+			(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
 #endif
 	timestamp = 0;		/* start "advancing" time stamp from 0 */
 
@@ -101,7 +102,7 @@ ulong get_timer_masked(void)
 	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 #else
 	ulong now = readl(&tmr->timer3_counter) /
-			(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+			(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
 #endif
 
 	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
@@ -155,7 +156,7 @@ void __udelay(unsigned long usec)
 #ifdef CONFIG_FTTMR010_EXT_CLK
 	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
 #else
-	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+	long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
 #endif
 	unsigned long now, last = readl(&tmr->timer3_counter);
 
@@ -190,7 +191,7 @@ ulong get_tbclk(void)
 #ifdef CONFIG_FTTMR010_EXT_CLK
 	return CONFIG_SYS_HZ;
 #else
-	return CONFIG_SYS_CLK_FREQ;
+	return get_board_sys_clk();
 #endif
 }
 #endif /* CONFIG_TIMER */

arch/powerpc/cpu/mpc83xx/pcie.c

@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <pci.h>
 #include <mpc83xx.h>
 #include <asm/global_data.h>
@@ -46,7 +47,7 @@ int get_pcie_clk(int index)
 
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 	sccr = im->clk.sccr;
-	pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+	pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
 	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 

arch/powerpc/cpu/mpc83xx/speed.c

@@ -137,8 +137,8 @@ int get_clocks(void)
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 
 	if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
+#if CONFIG_SYS_CLK_FREQ != 0
-		pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+		pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
 #else
 		pci_sync_in = 0xDEADBEEF;
 #endif

arch/powerpc/cpu/mpc83xx/spl_minimal.c

@@ -102,5 +102,5 @@ ulong get_bus_freq(ulong dummy)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 
-	return CONFIG_SYS_CLK_FREQ * spmf;
+	return get_board_sys_clk() * spmf;
 }

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -662,9 +662,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
-		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+		"clock-frequency", get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
-		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+		"clock-frequency", get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,mpic",
 		"clock-frequency", get_bus_freq(0)/2, 1);
 #else

arch/powerpc/cpu/mpc85xx/speed.c

@@ -75,7 +75,7 @@ void get_sys_info(sys_info_t *sys_info)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	uint mem_pll_rat;
 
 	sys_info->freq_systembus = sysclk;
@@ -102,7 +102,7 @@ void get_sys_info(sys_info_t *sys_info)
 	 * are driven by differential sysclock.
 	 */
 	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
-		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+		sys_info->freq_ddrbus = get_board_sys_clk();
 	else
 #endif
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
@@ -526,7 +526,7 @@ void get_sys_info(sys_info_t *sys_info)
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
-	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+	sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
 
 	/* Divide before multiply to avoid integer
 	 * overflow for processor speeds above 2GHz */
@@ -554,7 +554,7 @@ void get_sys_info(sys_info_t *sys_info)
 #else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
-	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+	sys_info->freq_qe = qe_ratio * get_board_sys_clk();
 #endif
 #endif
 

arch/sh/include/asm/config.h

@@ -11,6 +11,6 @@
 /* Timer */
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
 
 #endif

arch/xtensa/lib/time.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <time.h>
 #include <asm/global_data.h>
 #include <linux/delay.h>
@@ -51,7 +52,7 @@ static void delay_cycles(unsigned cycles)
 void __udelay(unsigned long usec)
 {
 	ulong lo, hi, i;
-	ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
+	ulong mhz = get_board_sys_clk() / 1000000;
 
 	/* Scale to support full 32-bit usec range */
 
@@ -74,7 +75,7 @@ ulong get_timer(ulong base)
 #if XCHAL_HAVE_CCOUNT
 	register ulong ccount;
 	__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
-	return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+	return ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
 #else
 	/*
 	 * Add at least the overhead of this call (in cycles).
@@ -85,7 +86,7 @@ ulong get_timer(ulong base)
 	 */
 
 	fake_ccount += 20;
-	return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+	return fake_ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
 #endif
 }
 
@@ -114,6 +115,6 @@ unsigned long timer_get_us(void)
 	unsigned long ccount;
 
 	__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
-	return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
+	return ccount / (get_board_sys_clk() / 1000000);
 }
 #endif

board/cadence/xtfpga/xtfpga.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <command.h>
 #include <dm.h>
 #include <init.h>

board/freescale/common/cadmus.c

@@ -5,7 +5,7 @@
 
 
 #include <common.h>
-
+#include <clock_legacy.h>
 
 /*
  * CADMUS Board System Registers

board/freescale/common/ics307_clk.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <log.h>
 #include <asm/io.h>
 

board/freescale/ls1043aqds/ls1043aqds.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <i2c.h>
 #include <fdt_support.h>
 #include <fsl_ddr_sdram.h>

board/freescale/ls1046aqds/ls1046aqds.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <i2c.h>
 #include <fdt_support.h>
 #include <fsl_ddr_sdram.h>

board/freescale/ls1088a/ls1088a.c

@@ -3,6 +3,7 @@
  * Copyright 2017-2018 NXP
  */
 #include <common.h>
+#include <clock_legacy.h>
 #include <env.h>
 #include <i2c.h>
 #include <init.h>

board/freescale/ls2080aqds/ls2080aqds.c

@@ -3,6 +3,7 @@
  * Copyright 2015 Freescale Semiconductor
  */
 #include <common.h>
+#include <clock_legacy.h>
 #include <env.h>
 #include <init.h>
 #include <malloc.h>

board/freescale/ls2080ardb/ls2080ardb.c

@@ -4,6 +4,7 @@
  * Copyright 2017 NXP
  */
 #include <common.h>
+#include <clock_legacy.h>
 #include <env.h>
 #include <init.h>
 #include <malloc.h>

board/freescale/p1010rdb/spl.c

@@ -43,7 +43,7 @@ void board_init_f(ulong bootflag)
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
 	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);

board/freescale/p1010rdb/spl_minimal.c

@@ -3,6 +3,7 @@
  * Copyright 2011 Freescale Semiconductor, Inc.
  */
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <mpc85xx.h>
 #include <asm/io.h>
@@ -29,7 +30,7 @@ void board_init_f(ulong bootflag)
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
 	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);

board/freescale/p1_p2_rdb_pc/spl.c

@@ -48,7 +48,7 @@ void board_init_f(ulong bootflag)
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
-	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	bus_clk = get_board_sys_clk() * plat_ratio;
 	gd->bus_clk = bus_clk;
 
 	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,

board/freescale/p1_p2_rdb_pc/spl_minimal.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <ns16550.h>
 #include <asm/io.h>
@@ -28,7 +29,7 @@ void board_init_f(ulong bootflag)
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
 	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);

board/freescale/p2041rdb/p2041rdb.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <command.h>
 #include <env.h>
 #include <fdt_support.h>

board/freescale/t102xrdb/spl.c

@@ -69,7 +69,7 @@ void board_init_f(ulong bootflag)
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = CONFIG_SYS_CLK_FREQ;
+	sys_clk = get_board_sys_clk();
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 

board/freescale/t104xrdb/spl.c

@@ -68,7 +68,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = CONFIG_SYS_CLK_FREQ;
+	sys_clk = get_board_sys_clk();
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	uart_clk = sys_clk * plat_ratio / 2;
 

board/freescale/t208xqds/t208xqds.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <command.h>
 #include <env.h>
 #include <fdt_support.h>

board/freescale/t208xrdb/spl.c

@@ -38,7 +38,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = CONFIG_SYS_CLK_FREQ;
+	sys_clk = get_board_sys_clk();
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 

board/freescale/t4rdb/spl.c

@@ -47,7 +47,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = CONFIG_SYS_CLK_FREQ;
+	sys_clk = get_board_sys_clk();
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 

board/renesas/eagle/eagle.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
@@ -50,7 +51,7 @@ void s_init(void)
 	writel(0xA5A5A500, &swdt->swtcsra);
 
 	/* CPU frequency setting. Set to 0.8GHz */
-	stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+	stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 }
 

board/renesas/gose/gose.c

@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <hang.h>
@@ -45,7 +46,7 @@ void s_init(void)
 	writel(0xA5A5A500, &swdt->swtcsra);
 
 	/* CPU frequency setting. Set to 1.5GHz */
-	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 
 	/* QoS */

board/renesas/koelsch/koelsch.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <hang.h>
@@ -47,7 +48,7 @@ void s_init(void)
 	writel(0xA5A5A500, &swdt->swtcsra);
 
 	/* CPU frequency setting. Set to 1.5GHz */
-	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 
 	/* QoS */

board/renesas/lager/lager.c

@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <env_internal.h>
@@ -50,7 +51,7 @@ void s_init(void)
 	/* CPU frequency setting. Set to 1.4GHz */
 	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
 		u32 stat = 0;
-		u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+		u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
 			<< PLL0_STC_BIT;
 		clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 

board/renesas/porter/porter.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <hang.h>
@@ -47,7 +48,7 @@ void s_init(void)
 	writel(0xA5A5A500, &swdt->swtcsra);
 
 	/* CPU frequency setting. Set to 1.5GHz */
-	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
 	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 
 	/* QoS */

board/renesas/stout/stout.c

@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <env.h>
 #include <init.h>
 #include <malloc.h>
@@ -50,7 +51,7 @@ void s_init(void)
 	/* CPU frequency setting. Set to 1.4GHz */
 	if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
 		u32 stat = 0;
-		u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+		u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
 			<< PLL0_STC_BIT;
 		clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
 

board/socrates/socrates.c

@@ -57,7 +57,7 @@ int checkboard (void)
 	/* Check the PCI_clk sel bit */
 	if (in_be32(&gur->porpllsr) & (1<<15)) {
 		src = "SYSCLK";
-		f = CONFIG_SYS_CLK_FREQ;
+		f = get_board_sys_clk();
 	} else {
 		src = "PCI_CLK";
 		f = CONFIG_PCI_CLK_FREQ;

board/sunxi/board.c

@@ -11,6 +11,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <dm.h>
 #include <env.h>
 #include <hang.h>
@@ -667,7 +668,7 @@ void sunxi_board_init(void)
 	 * assured it's being powered with suitable core voltage
 	 */
 	if (!power_failed)
-		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
+		clock_set_pll1(get_board_sys_clk());
 	else
 		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }

board/xes/common/fsl_8xxx_clk.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <asm/io.h>
 
 /*

boot/Kconfig

@@ -358,11 +358,27 @@ config SYS_TEXT_BASE
 	help
 	  The address in memory that U-Boot will be running from, initially.
 
-config SYS_CLK_FREQ
+config DYNAMIC_SYS_CLK_FREQ
-	depends on ARC || ARCH_SUNXI || MPC83xx
+	bool "Determine CPU clock frequency at run-time"
-	int "CPU clock frequency"
 	help
-	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+	  Implement a get_board_sys_clk function that will determine the CPU
+	  clock frequency at run time, rather than define it statically.
+
+config SYS_CLK_FREQ
+	depends on !DYNAMIC_SYS_CLK_FREQ
+	int "CPU clock frequency"
+	default 125000000 if ARCH_LS1012A
+	default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
+			     ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+	default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
+	default 66660000 if ARCH_T2080
+	default 33333333 if RCAR_GEN3
+	default 24000000 if ARCH_EXYNOS
+	default 20000000 if RCAR_GEN2
+	default 0
+	help
+	  A static value for the CPU frequency.  Note that if not required
+	  for a given SoC, this can be left at 0.
 
 config ARCH_FIXUP_FDT_MEMORY
 	bool "Enable arch_fixup_memory_banks() call"

configs/MPC8548CDS_36BIT_defconfig

@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_PHYS_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/MPC8548CDS_defconfig

@@ -10,6 +10,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/MPC8548CDS_legacy_defconfig

@@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/P2041RDB_NAND_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"

configs/P2041RDB_SDCARD_defconfig

@@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"

configs/P2041RDB_SPIFLASH_defconfig

@@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"

configs/P2041RDB_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/P3041DS_NAND_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"

configs/P3041DS_SDCARD_defconfig

@@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"

configs/P3041DS_SPIFLASH_defconfig

@@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"

configs/P3041DS_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/P4080DS_SDCARD_defconfig

@@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"

configs/P4080DS_SPIFLASH_defconfig

@@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"

configs/P4080DS_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/P5040DS_NAND_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"

configs/P5040DS_SDCARD_defconfig

@@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"

configs/P5040DS_SPIFLASH_defconfig

@@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"

configs/P5040DS_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"

configs/T2080QDS_NAND_defconfig

@@ -22,6 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"

configs/T2080QDS_SDCARD_defconfig

@@ -22,6 +22,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"

configs/T2080QDS_SECURE_BOOT_defconfig

@@ -16,6 +16,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"

configs/T2080QDS_SPIFLASH_defconfig

@@ -24,6 +24,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"

configs/T2080QDS_SRIO_PCIE_BOOT_defconfig

@@ -15,6 +15,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"

configs/T2080QDS_defconfig

@@ -15,6 +15,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"

configs/adp-ae3xx_defconfig

@@ -7,6 +7,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
+CONFIG_SYS_CLK_FREQ=39062500
 CONFIG_TARGET_ADP_AE3XX=y
 CONFIG_SYS_LOAD_ADDR=0x300000
 CONFIG_FIT=y

configs/adp-ag101p_defconfig

@@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_SYS_CLK_FREQ=39062500
 CONFIG_TARGET_ADP_AG101P=y
 CONFIG_SYS_LOAD_ADDR=0x300000
 CONFIG_FIT=y

configs/armadillo-800eva_defconfig

@@ -11,6 +11,7 @@ CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
 CONFIG_R8A7740=y
 CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_SYS_CLK_FREQ=50000000
 CONFIG_SYS_LOAD_ADDR=0x44000000
 CONFIG_BOOTDELAY=3
 # CONFIG_CMDLINE_EDITING is not set

configs/da850evm_defconfig

@@ -24,6 +24,7 @@ CONFIG_SPL_SPI=y
 CONFIG_LTO=y
 CONFIG_SYS_LOAD_ADDR=0xc0700000
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "

configs/da850evm_direct_nor_defconfig

@@ -15,6 +15,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
 CONFIG_LTO=y
 CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"

configs/da850evm_nand_defconfig

@@ -22,6 +22,7 @@ CONFIG_SPL_SPI=y
 CONFIG_LTO=y
 CONFIG_SYS_LOAD_ADDR=0xc0700000
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "

configs/grpeach_defconfig

@@ -10,6 +10,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
 CONFIG_RZA1=y
+CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_SYS_LOAD_ADDR=0x20400000
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y

configs/kmcent2_defconfig

@@ -7,6 +7,7 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
 CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_SYS_CLK_FREQ=66666666
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

configs/legoev3_defconfig

@@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
 CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=0
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"

configs/ls1021aqds_ddr4_nor_defconfig

@@ -20,6 +20,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/ls1021aqds_ddr4_nor_lpuart_defconfig

@@ -21,6 +21,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/ls1021aqds_nand_defconfig

@@ -28,6 +28,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"

configs/ls1021aqds_nor_SECURE_BOOT_defconfig

@@ -21,6 +21,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/ls1021aqds_nor_defconfig

@@ -20,6 +20,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/ls1021aqds_nor_lpuart_defconfig

@@ -21,6 +21,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/ls1021aqds_sdcard_ifc_defconfig

@@ -26,6 +26,7 @@ CONFIG_AHCI=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"

configs/ls1043aqds_defconfig

@@ -23,6 +23,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"

configs/ls1043aqds_lpuart_defconfig

@@ -24,6 +24,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"

configs/ls1043aqds_nand_defconfig

@@ -30,6 +30,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg"

configs/ls1043aqds_nor_ddr3_defconfig

@@ -23,6 +23,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"

configs/ls1043aqds_qspi_defconfig

@@ -24,6 +24,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y

configs/ls1043aqds_sdcard_ifc_defconfig

@@ -30,6 +30,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg"

configs/ls1043aqds_sdcard_qspi_defconfig

@@ -30,6 +30,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg"

configs/ls1043aqds_tfa_SECURE_BOOT_defconfig

@@ -25,6 +25,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"

configs/ls1043aqds_tfa_defconfig

@@ -26,6 +26,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"

configs/ls1046aqds_SECURE_BOOT_defconfig

@@ -23,6 +23,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"

configs/ls1046aqds_defconfig

@@ -23,6 +23,7 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"

configs/ls1046aqds_lpuart_defconfig

@@ -24,6 +24,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"