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Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

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- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
This commit is contained in:
Tom Rini
2022-06-20 08:09:24 -04:00
parent a9e90d357b eae488b779
commit 2f7821a927
69 changed files with 2296 additions and 761 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/clk/Kconfig
View File

@@ -166,22 +166,6 @@ config CLK_SCMI
by a SCMI agent based on SCMI clock protocol communication
with a SCMI server.
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
default y
help
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP1"
depends on ARCH_STM32MP && CLK
default y
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
@@ -251,6 +235,7 @@ source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"

5
drivers/clk/Makefile
View File

@@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_ARCH_STM32) += stm32/
obj-$(CONFIG_ARCH_STM32MP) += stm32/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
@@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
@@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o

23
drivers/clk/stm32/Kconfig Normal file
View File

@@ -0,0 +1,23 @@
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
default y
help
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
config CLK_STM32H7
bool "Enable clock driver support for STM32H7 family"
depends on CLK && STM32H7
default y
help
This clock driver adds support for RCC clock management
for STM32H7 SoCs.
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP15"
depends on ARCH_STM32MP && CLK
default y if STM32MP15x
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP15's on-SoC clocks.

7
drivers/clk/stm32/Makefile Normal file
View File

@@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2022, STMicroelectronics - All Rights Reserved
obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o

0
drivers/clk/clk_stm32f.c → drivers/clk/stm32/clk-stm32f.c
View File

0
drivers/clk/clk_stm32h7.c → drivers/clk/stm32/clk-stm32h7.c
View File

0
drivers/clk/clk_stm32mp1.c → drivers/clk/stm32/clk-stm32mp1.c
View File

2
drivers/i2c/designware_i2c.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
#include <common.h>

2
drivers/i2c/designware_i2c.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
#ifndef __DW_I2C_H_

2
drivers/i2c/designware_i2c_pci.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
* Copyright 2019 Google Inc
*/

6
drivers/misc/stm32_rcc.c
View File

@@ -39,6 +39,11 @@ struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
.soc = STM32MP1,
};
struct stm32_rcc_clk stm32_rcc_clk_mp13 = {
.drv_name = "stm32mp13_clk",
.soc = STM32MP1,
};
static int stm32_rcc_bind(struct udevice *dev)
{
struct udevice *child;
@@ -79,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = {
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
{.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 },
{ }
};

14
drivers/mmc/stm32_sdmmc2.c
View File

@@ -514,10 +514,12 @@ retry_cmd:
*/
static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
{
/* Reset */
reset_assert(&priv->reset_ctl);
udelay(2);
reset_deassert(&priv->reset_ctl);
if (reset_valid(&priv->reset_ctl)) {
/* Reset */
reset_assert(&priv->reset_ctl);
udelay(2);
reset_deassert(&priv->reset_ctl);
}
/* init the needed SDMMC register after reset */
writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
@@ -735,7 +737,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
if (ret)
goto clk_disable;
dev_dbg(dev, "No reset provided\n");
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
GPIOD_IS_IN);
@@ -755,8 +757,6 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
stm32_sdmmc2_reset(priv);
return 0;
clk_disable:
clk_disable(&priv->clk);
clk_free:
clk_free(&priv->clk);

4
drivers/mtd/nand/raw/fsmc_nand.c
View File

@@ -1,10 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*
* (C) Copyright 2012
* Amit Virdi, ST Microelectronics, amit.virdi@st.com.
* Amit Virdi, STMicroelectronics, amit.virdi@st.com.
*/
#include <common.h>

2
drivers/mtd/spi/spi-nor-ids.c
View File

@@ -280,7 +280,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* ST Microelectronics -- newer production may have feature updates */
/* STMicroelectronics -- newer production may have feature updates */
{ INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
{ INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
{ INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },

2
drivers/net/designware.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
/*

2
drivers/net/designware.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
#ifndef _DW_ETH_H

2
drivers/pinctrl/Kconfig
View File

@@ -272,7 +272,7 @@ config PINCTRL_STI
depends on DM && ARCH_STI
default y
help
Support pin multiplexing control on STMicrolectronics STi SoCs.
Support pin multiplexing control on STMicroelectronics STi SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available

1
drivers/pinctrl/pinctrl_stm32.c
View File

@@ -488,6 +488,7 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
{ .compatible = "st,stm32h743-pinctrl" },
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },
{ .compatible = "st,stm32mp135-pinctrl" },
{ }
};

28
drivers/ram/stm32mp1/stm32mp1_ram.c
View File

@@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
reg = readl(&ctl->addrmap3);
/* addrmap3.addrmap_col_b6 */
val = (reg & GENMASK(3, 0)) >> 0;
val = (reg & GENMASK(4, 0)) >> 0;
if (val <= 7)
bits++;
/* addrmap3.addrmap_col_b7 */
val = (reg & GENMASK(11, 8)) >> 8;
val = (reg & GENMASK(12, 8)) >> 8;
if (val <= 7)
bits++;
/* addrmap3.addrmap_col_b8 */
val = (reg & GENMASK(19, 16)) >> 16;
val = (reg & GENMASK(20, 16)) >> 16;
if (val <= 7)
bits++;
/* addrmap3.addrmap_col_b9 */
val = (reg & GENMASK(27, 24)) >> 24;
val = (reg & GENMASK(28, 24)) >> 24;
if (val <= 7)
bits++;
reg = readl(&ctl->addrmap4);
/* addrmap4.addrmap_col_b10 */
val = (reg & GENMASK(3, 0)) >> 0;
val = (reg & GENMASK(4, 0)) >> 0;
if (val <= 7)
bits++;
/* addrmap4.addrmap_col_b11 */
val = (reg & GENMASK(11, 8)) >> 8;
val = (reg & GENMASK(12, 8)) >> 8;
if (val <= 7)
bits++;
@@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
reg = readl(&ctl->addrmap6);
/* addrmap6.addrmap_row_b12 */
val = (reg & GENMASK(3, 0)) >> 0;
if (val <= 7)
if (val <= 11)
bits++;
/* addrmap6.addrmap_row_b13 */
val = (reg & GENMASK(11, 8)) >> 8;
if (val <= 7)
if (val <= 11)
bits++;
/* addrmap6.addrmap_row_b14 */
val = (reg & GENMASK(19, 16)) >> 16;
if (val <= 7)
if (val <= 11)
bits++;
/* addrmap6.addrmap_row_b15 */
val = (reg & GENMASK(27, 24)) >> 24;
if (val <= 7)
if (val <= 11)
bits++;
if (reg & BIT(31))
printf("warning: LPDDR3_6GB_12GB is not supported\n");
return bits;
}
@@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = {
.get_info = stm32mp1_ddr_get_info,
};
static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = {
.nb_bytes = 2,
};
static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
.nb_bytes = 4,
};
static const struct udevice_id stm32mp1_ddr_ids[] = {
{ .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
{ .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg},
{ }
};

2
drivers/spi/pl022_spi.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012
* Armando Visconti, ST Microelectronics, armando.visconti@st.com.
* Armando Visconti, STMicroelectronics, armando.visconti@st.com.
*
* (C) Copyright 2018
* Quentin Schulz, Bootlin, quentin.schulz@bootlin.com

2
drivers/usb/gadget/designware_udc.c
View File

@@ -4,7 +4,7 @@
* TI OMAP1510 USB bus interface driver
*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
#include <common.h>