[MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros
This patch replaces the current function definitions with NESTED, LEAF and END macro. They specify some more additional information about the function; an alignment of symbol, type of symbol, stack frame usage, etc. These information explicitly tells the assembler and the debugger about the types of code we want to generate. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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@@ -24,6 +24,7 @@
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#include <config.h>
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#include <version.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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@@ -119,10 +120,7 @@
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* RETURNS: N/A
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*
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*/
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.globl mips_cache_reset
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.ent mips_cache_reset
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mips_cache_reset:
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NESTED(mips_cache_reset, 0, ra)
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li t2, CFG_ICACHE_SIZE
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li t3, CFG_DCACHE_SIZE
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li t4, CFG_CACHELINE_SIZE
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@@ -198,8 +196,7 @@ mips_cache_reset:
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icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
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j ra
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.end mips_cache_reset
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END(mips_cache_reset)
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/*******************************************************************************
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*
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@@ -208,15 +205,11 @@ mips_cache_reset:
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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.globl dcache_status
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.ent dcache_status
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dcache_status:
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LEAF(dcache_status)
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mfc0 v0, CP0_CONFIG
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andi v0, v0, 1
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j ra
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.end dcache_status
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END(dcache_status)
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/*******************************************************************************
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*
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@@ -225,18 +218,14 @@ dcache_status:
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* RETURNS: N/A
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*
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*/
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.globl dcache_disable
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.ent dcache_disable
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dcache_disable:
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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j ra
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.end dcache_disable
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END(dcache_disable)
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#ifdef CFG_INIT_RAM_LOCK_MIPS
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/*******************************************************************************
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